Semiconductor memory device having a short reset time

• US 20080186792A1
• Filed: 02/01/2008
• Published: 08/07/2008
• Est. Priority Date: 02/07/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Na, Byong-Wook, Cheon, Kwun-Soo
• Granted Patent: US 7,764,562 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit is initialized in response to the column reset signal. The semiconductor memory device can reduce a peak value of a surge current by initializing a row path circuit and a column path circuit at different time points. Therefore, the semiconductor memory device may have a relatively short setup time of an internal power supply voltage.

Claims

1. A semiconductor memory device, comprising:

a row path circuit configured to decode a row address signal to provide a word line enable signal to a memory cell array, the row path circuit configured to be initialized in response to a power-up signal;

a reset signal generating circuit configured to delay the power-up signal to generate a column reset signal; and

a column path circuit configured to decode a column address signal to provide a column selection signal to the memory cell array, the column path circuit configured to be initialized in response to the column reset signal.

2. The semiconductor memory device of claim 1, wherein the row path circuit and the column path circuit are initialized at different time points.

3. The semiconductor memory device of claim 2, wherein the row path circuit is initialized in a power-up region and the column path circuit is initialized in a mode setting region of the device.

4. The semiconductor memory device of claim 2, wherein the row path circuit is initialized in a power-up region and the column path circuit is initialized in an auto refresh region of the device.

5. The semiconductor memory device of claim 1, wherein the reset signal generating circuit comprises:

a pulse generator configured to generate a control pulse in response to a command signal; and

a switching circuit configured to transfer the power-up signal to a first node in response to the control pulse.

6. The semiconductor memory device of claim 5, wherein the reset signal generating circuit further comprises:

an inverter configured to invert the power-up signal; and

a transistor configured to provide a reference voltage to the first node in response to an output signal of the inverter.

7. The semiconductor memory device of claim 6, wherein the reset signal generating circuit further comprises a latch circuit configured to latch a voltage signal of the first node to output the column reset signal.

8. The semiconductor memory device of claim 5, wherein the pulse generator comprises:

a NOR logic unit configured to perform an NOR operation on the command signal, including a chip selection signal, a row address strobe signal, a column address strobe signal and a write enable signal;

a delay circuit configured to delay a first output signal of the NOR logic unit such that the control pulse has a pulse width corresponding to a delay time generated by the delay circuit; and

an AND logic unit configured to perform an AND operation on the first output signal and a second output signal of the delay circuit to output the control pulse.

9. The semiconductor memory device of claim 8, wherein the pulse generator is configured to generate the control pulse in a mode setting region of the device.

10. The semiconductor memory device of claim 8, wherein the pulse generator is configured to generate the control pulse when the chip selection signal, the row address strobe signal, the column address strobe signal and the write enable signal are enabled.

11. The semiconductor memory device of claim 5, wherein the pulse generator comprises:

an inverter configured to invert a write enable signal;

a NOR logic unit configured to perform an NOR operation on the command signal, including a chip selection signal, a row address strobe signal, a column address strobe signal and a first output signal of the inverter;

a delay circuit configured to delay a second output signal of the NOR logic unit such that the control pulse has a pulse width corresponding to a delay time generated by the delay circuit; and

an AND logic unit configured to perform an AND operation on the second output signal and a third output signal of the delay circuit to output the control pulse.

12. The semiconductor memory device of claim 11, wherein the pulse generator is configured to generate the control pulse in an auto refresh region of the device.

13. The semiconductor memory device of claim 11, wherein the pulse generator is configured to generate the control pulse when the chip selection signal, the row address strobe signal and the column address strobe signal are enabled and the write enable signal is disabled.

14. The semiconductor memory device of claim 1, wherein the reset signal generating circuit comprises:

a switching circuit configured to transfer the power-up signal to a first node in response to a control pulse;

a latch circuit configured to latch a voltage signal of the first node;

a first inverter configured to invert an output signal of the latch circuit to output the column reset signal; and

a pulse generator configured to generate the control pulse in response to a command signal and the column reset signal.

15. The semiconductor memory device of claim 14, wherein the reset signal generating circuit further comprises:

an inverter configured to invert the power-up signal; and

a transistor configured to provide a reference voltage to the first node in response to an output signal of the inverter.

16. The semiconductor memory device of claim 14, wherein the pulse generator comprises:

a NOR logic unit configured to perform an NOR operation on the command signal, including a chip selection signal, a row address strobe signal, a column address strobe signal and a write enable signal;

a delay circuit configured to delay a first output signal of the NOR logic unit such that the control pulse has a pulse width corresponding to a delay time generated by the delay circuit; and

an AND logic unit configured to perform an AND operation on the first output signal and a second output signal of the delay circuit to output the control pulse.

17. The semiconductor memory device of claim 16, wherein the pulse generator is configured to generate the control pulse in a mode setting region of the device.

18. The semiconductor memory device of claim 16, wherein the pulse generator is configured to generate the control pulse when the chip selection signal, the row address strobe signal, the column address strobe signal and the write enable signal are enabled.

19. The semiconductor memory device of claim 14, wherein the pulse generator comprises:

an inverter configured to invert a write enable signal;

a NOR logic unit configured to perform an NOR operation on the command signal, including a chip selection signal, a row address strobe signal, a column address strobe signal and a first output signal of the inverter;

a delay circuit configured to delay a second output signal of the NOR logic unit such that the control pulse has a pulse width corresponding to a delay time generated by the delay circuit; and

an AND logic unit configured to perform an AND operation on the second output signal and a third output signal of the delay circuit to output the control pulse.

20. The semiconductor memory device of claim 19, wherein the pulse generator is configured to generate the control pulse in an auto refresh region of the device.

21. The semiconductor memory device of claim 19, wherein the pulse generator is configured to generate the control pulse when the chip selection signal, the row address strobe signal and the column address strobe signal are enabled and the write enable signal is disabled.

22. The semiconductor memory device of claim 1, further comprising:

an address input buffer configured to generate the row address signal and the column address signal in response to an external address signal; and

a power-up circuit configured to generate the power-up signal based on an external power supply voltage.

23. The semiconductor memory device of claim 1, wherein the row path circuit includes a row decoder and the column path circuit includes a column decoder.