Device for generating counter signals representative of clock signals and device for reconstructing clock signals, for a packet-switched network

• US 20080187083A1
• Filed: 02/05/2008
• Published: 08/07/2008
• Est. Priority Date: 02/06/2007
• Status: Active Grant

• Current Assignee: Magnolia Licensing LLC (IP Edge LLC)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Tapie, Thierry, Defrance, Serge, Montalvo, Luis
• Granted Patent: US 8,611,371 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/4302 Content synchronisation processes, e.g. decoder synchronisation
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083

Abstract

A device (D2) is dedicated to the reconstruction of clock signals, for example within communication equipment (EQ2) of an IP network. This device (D2) comprises i) a phase-locked loop (BV) having a cut-off frequency dependent, on the one hand, on a configuration value making it possible to reconstruct clock signals according to a chosen clock frequency, and on the other hand, a chosen sampling frequency, and ii) control means (MC2) responsible for forcing the phase-locked loop (BV) to present a variable cut-off frequency according to a received operating mode indication.

Claims

1. Device (D1) for generating counter signals representative of clock signals, said device (D1) comprising i) clock means (MH1) arranged to deliver clock signals according to a so-called reference clock frequency, ii) a counter (C1) arranged to deliver a signal of periodic ramp representative of the number of clock signals delivered, and iii) a sampler (E1) arranged to sample said ramp signal at a chosen sampling frequency to form counter signals, wherein said clock means (MH1) are arranged to deliver clock signals according to at least one other clock frequency differing from said reference clock frequency, and in that it comprises control means (MC1) arranged to select one of the deliverable clock frequencies according to a received command and to define a sampling frequency equal to a reference sampling frequency multiplied by the value of the ratio between the selected clock frequency and the reference clock frequency.

2. Device according to claim 1, wherein said clock means (MH1) are arranged to deliver clock signals according to at least one other clock frequency, of which the ratio with said reference clock frequency is equal to a chosen power of two.

3. Device according to claim 1, wherein said clock means (MH1) comprise at least first (H1) and second (H2) clocks arranged to deliver to outputs clock signals respectively having said reference clock frequency and said other clock frequency, and in that it comprises selection means (MS) comprising first and second inputs connected respectively to the outputs of the first (H1) and second (H2) clocks, and an output connected to the input of said counter (C1) and specifically for being connected, selectively and on command from said control means (MC1), either to said first input or to said second input so as to deliver clock signals having either said reference clock frequency or said other clock frequency.

4. Device according to claim 2, wherein said clock means (MH1) comprise at least first (H1) and second (H2) clocks arranged to deliver to outputs clock signals respectively having said reference clock frequency and said other clock frequency, and in that it comprises selection means (MS) comprising first and second inputs connected respectively to the outputs of the first (H1) and second (H2) clocks, and an output connected to the input of said counter (C1) and specifically for being connected, selectively and on command from said control means (MC1), either to said first input or to said second input so as to deliver clock signals having either said reference clock frequency or said other clock frequency.

5. Device according to claim 1, wherein it comprises network interface means (MI1) connected to the output of said sampler (E1) and arranged to form data packets addressed to remote communication equipment (EQ2) and comprising said delivered counter signals and an indication signalling an operating mode defined by the selected clock frequency and sampling frequency defined by said control means (MC1).

6. Device according to claim 5, wherein said network interface means (MI1) are arranged to place, in a packet to be transmitted, a counter field, of which the most significant bit represents said operating mode indication and the other lower-order bits represent the last counter signal delivered by said sampler (E1).

7. Communication equipment (EQ1) for a packet-switched communication network specifically for transmitting packet frames, wherein it comprises a device for generating counter signals (D1) according to claim 1.

8. Device for reconstructing clock signals (D2), comprising a phase-locked loop (BV) having a cut-off frequency dependent on i) a configuration value making it possible to reconstruct clock signals according to a chosen clock frequency, and ii) a chosen sampling frequency, said device comprising control means (MC2) arranged to force said phase-locked loop (BV) to present a variable cut-off frequency according to a received operating mode indication, wherein said phase-locked loop (BV) comprises i) comparison means (MCN) arranged to compare an external counter signal with a local counter signal and to deliver a comparison signal representative of the result of said comparison, ii) correction means (MCR) arranged to determine said configuration value from said comparison signal, iii) clock means (MH2) arranged to deliver clock signals according to the clock frequency defined by said configuration value, iv) a counter (C2) arranged to deliver a signal of periodic ramp representative of the number of clock signals delivered by said clock means (MH2), and v) a sampler (E2) arranged to sample said ramp signal according to the chosen sampling frequency to deliver said local counter signal, and in that said control means (MC2) are arranged to configure said correction means (MCR) so that they generate a configuration value forcing said clock means (MH2) to deliver clock signals having a clock frequency equal to a reference clock frequency multiplied by a ratio value dependent on a received operating mode indication, and to define for said sampler (E2) a chosen sampling frequency, equal to a reference sampling frequency multiplied by said ratio value.

9. Device according to in claim 8, wherein said ratio value is equal to the result of the division of the clock frequency defined by the configuration value resulting from the configuration by a reference clock frequency.

10. Device according to claim 8, wherein said ratio value is equal to a chosen power of two.

11. Device according to claim 9, wherein said ratio value is equal to a chosen power of two.

12. Device according to claim 8, wherein it comprises network interface means (MI2) connected to the input of said phase-locked loop (BV) and arranged to receive frames of data packets comprising said external counter signals and said operating mode indication.

13. Device according to claim 12, wherein, in the presence of received packets containing a counter field, of which the most significant bit represents said operating mode indication and the other lower-order bits represent an external counter signal, said network interface means (MI2) are arranged to determine the value of the most significant bit in each received packet containing a counter field and to transmit this most significant bit value to said control means (MC2).

14. Communication equipment (EQ2) for a packet-switched communication network specifically for transmitting packet frames, wherein it comprises a device for reconstructing clock signals (D2) according to claim 8.