SEMICONDUCTOR DEVICE AND SHIFT REGISTER CIRCUIT

• US 20080187089A1
• Filed: 01/02/2008
• Published: 08/07/2008
• Est. Priority Date: 02/07/2007
• Status: Active Grant

• Current Assignee: Trivale Technologies, LLC (Vector Capital Corporation)
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Tobita, Youichi, Murai, Hiroyuki, Miyayama, Takashi, Mori, Seiichiro
• Granted Patent: US 8,023,610 B2
• Time in Patent Office: Days
• US Class Current: 377/79
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

Claims

1. A semiconductor device comprising a plurality of first transistors connected in series between predetermined first and second nodes, said plurality of first transistors each having a control electrode connected to each other, wherein

each of connection nodes between said plurality of first transistors is a third node, and

when said control electrode changes from an H (High) level higher than a threshold voltage of said plurality of first transistors where each of said first to third nodes and said control electrode is the H level to an L (low) level lower than said threshold voltage while said first and second nodes are kept at the H level, said third node is pulled down to the L level accordingly.

2. The semiconductor device according to claim 1, wherein

means for pulling down said third node in level is a parasitic capacitance between said control electrode and said third node.

3. The semiconductor device according to claim 2, wherein

an electrode to be said third node has a greater width than electrodes to be said first and second nodes.

4. The semiconductor device according to claim 2, wherein

in said third node, C1≧

C2×

(Vd−

Vth)/Vth holds where C1 denotes a capacitive component between said control electrode and said third node, C2 denotes a parasitic capacitance accompanied with said third node not contained in C1, Vd denotes a difference between the H level and L level in said control electrode, and Vth denotes the threshold voltage of said plurality of first transistors.

5. The semiconductor device according to claim 1, further comprising a capacitive element connected between said control electrode and said third node, as means for pulling down said third node in level.

6. The semiconductor device according to claim 5, wherein in said third node, C1≧

C2×

(Vd−

Vth)/Vth holds where C1 denotes a capacitive component between said control electrode and said third node, C2 denotes a parasitic capacitance accompanied with said third node not contained in C1, Vd denotes a difference between the H level and L level in said control electrode, and Vth denotes the threshold voltage of said plurality of first transistors.

7. The semiconductor device according to claim 1, further comprising a diode connected between said control electrode and said third node such that said control electrode serves as a cathode and said third node serves as an anode, as means for pulling down said third node in level.

8. The semiconductor device according to claim 1, further comprising

a second transistor connected between said control electrode of said plurality of first transistors and said third node, as means for pulling down said third node in level.

9. The semiconductor device according to claim 1, wherein

said plurality of first transistors are amorphous silicon thin-film transistors.

10. The semiconductor device according to claim 1, wherein

said plurality of first transistors are organic transistors.

11. A shift register comprising:

an input terminal, an output terminal, a first clock terminal and a reset terminal;

a first transistor configured to supply a first clock signal received at said first clock terminal to said output terminal;

a second transistor configured to discharge said output terminal;

a charging circuit configured to charge a first node to which a control electrode of said first transistor is connected, in accordance with an input signal received at said input terminal; and

a discharging circuit configured to discharge said first node in accordance with a reset signal received at said reset terminal, wherein

said charging circuit includes a plurality of third transistors connected in series between said first node and a power terminal and having control electrodes connected in common to said input terminal.

12. The shift register according to claim 11, wherein

said charging circuit is configured to turn on said plurality of third transistors when said input signal reaches an H (High) level higher than a threshold voltage of said plurality of third transistors, to thereby charge said first node, and then to pull down each connection node between said plurality of third transistors to an L (Low) level lower than said threshold voltage when the input signal changes to the L level.

13. The shift register according to claim 11, wherein

said second transistor has a control electrode connected to said reset terminal.

14. The shift register according to claim 11, further comprising

an inverter with said first node serving as its input node and a second node connected to the control electrode of said second transistor serving as its output node.

15. The shift register according to claim 14, further comprising

a fourth transistor having a control electrode connected to said second node and configured to discharge said first node.

16. The shift register according to claim 11, wherein

said second transistors includes two second transistors,

control electrodes of said two second transistors are connected to second and third nodes, respectively, and

said two second transistors are driven alternately on the basis of a predetermined control signal.

17. The shift register according to claim 16, wherein

said control signal is made up of first and second control signals complementary to each other,

said shift register further comprising:

first and second control terminals receiving said first and second control signals, respectively;

a fourth transistor connected between said first control terminal and said second node; and

a fifth transistor connected between said second control terminal and said third node, wherein

said fourth and fifth transistors each having one main electrode connected to a control electrode of each other in a crossed manner.

18. The shift register according to claim 16, wherein

means for driving said two second transistors alternately includes:

an inverter with said first node serving as its input node; and

a switching circuit configured to connect an output node of said inverter to said second and third nodes alternately on the basis of said control signal.

19. The shift register according to claim 16, further comprising:

a sixth transistor having a control electrode connected to said second node and configured to discharge said first node; and

a seventh transistor having a control electrode connected to said third node and configured to discharge said first node.

20. The shift register according to claim 11, further comprising

a fourth transistor connected between said first node and said output terminal and having a control electrode connected to said first clock terminal.

21. The shift register according to claim 20, further comprising:

a second clock terminal receiving a second clock signal of different phase from said first clock signal;

an inverter with said first node serving as its input node, being activated by said second clock signal;

a fifth transistor having a control electrode connected to said first clock terminal and configured to discharge an output node of said inverter; and

a sixth transistor having a control electrode connected to the output node of said inverter and configured to discharge said first node.

22. The shift register according to claim 21, wherein

said second transistor has a control electrode connected to said second clock terminal.

23. The shift register according to claim 22, wherein

said second transistor is connected between said output terminal and said first clock terminal.

24. The shift register according to claim 11, further comprising:

an inverter with said first node serving as its input node, being activated by said first clock signal; and

a fourth transistor having a control electrode connected to an output node of said inverter and configured to discharge said first node, wherein

said inverter includes a first capacitive element connected between said output node of said inverter and said first clock terminal, as a loading element.

25. The shift register according to claim 24, wherein

said second transistor has a control electrode connected to said output node of said inverter.

26. The shift register according to claim 25, further comprising:

a second clock terminal receiving a second clock signal of different phase from said first clock signal; and

a fifth transistor having a control electrode connected to said second clock terminal and configured to discharge said output terminal.

27. The shift register according to claim 11, further comprising

a second capacitive element connected between each connection node of said plurality of third transistors and said input terminal.

28. The shift register according to claim 11, further comprising

a diode connected between each connection node of said plurality of third transistors and said input terminal such that said input terminal serves as a cathode and said connection node serves as an anode.

29. The shift register according to claim 11, further comprising

a sixth transistor connected between each connection node of said plurality of third transistors and said input terminal and having a control electrode connected to said first clock terminal.

30. A shift register comprising:

first and second input terminals, an output terminal, a first clock terminal and a reset terminal;

a first transistor configured to supply a first clock signal received at said first clock terminal to said output terminal;

a second transistor configured to discharge said output terminal;

a first charging circuit configured to charge a first node to which a control electrode of said first transistor is connected; and

a first discharging circuit configured to discharge said first node in accordance with a reset signal received at said reset terminal, wherein said first charging circuit includes;

a plurality of third transistors connected in series between said first node and a power terminal and having control electrodes connected in common to a predetermined second node;

a second charging circuit configured to charge said second node in accordance with a first input signal received at said first input terminal;

a step-up circuit configured to step-up said second node in accordance with a second input signal received at said second input terminal; and

a second discharging circuit configured to discharge said second node in accordance with said reset signal.

31. The shift register according to claim 30, wherein

said first charging circuit is configured to turn on said plurality of third transistors when said second node reaches an H (High) level higher than a threshold voltage of said plurality of third transistors, to thereby charge said first node, and then to pull down each connection node between said plurality of third transistors to an L (Low) level lower than said threshold voltage when said second node changes to the L level.

32. The shift register according to claim 30, further comprising

an inverter with said second node serving as its input node, wherein

said first discharging circuit is a fourth transistor having a control electrode connected to an output node of said inverter and configured to discharge said first node.

33. The shift register according to claim 32, further comprising

a fifth transistor having a control electrode connected to an output node of said inverter and configured to discharge said second node.

34. The shift register according to claim 32, wherein

said second transistor has a control electrode connected to said output node of said inverter.

35. The shift register according to claim 30, further comprising

a capacitive element connected between each connection node of said plurality of third transistors and said second node.

36. The shift register according to claim 30, further comprising

a diode connected between each connection node of said plurality of third transistors and said second node such that said second node serves as a cathode and said connection node serves as an anode.

37. The shift register according to claim 30, further comprising

a sixth transistor between each connection node of said plurality of third transistors and said second node, having a control electrode connected to said first clock terminal.

38. The shift register according to claim 30, wherein

said second charging circuit includes a plurality of seventh transistors connected in series between said second node and a power terminal and having control electrodes connected in common to said first input terminal.

39. The shift register according to claim 38, wherein

said second charging circuit is configured to turn on said plurality of seventh transistors when said first input terminal reaches an H (High) level higher than a threshold voltage of said plurality of seventh transistors, to thereby charge said second node, and then to pull down each connection node between said plurality of seventh transistors to an L (Low) level lower than said threshold voltage when the first input terminal changes to the L level.

40. The shift register according to claim 38, further comprising

a capacitive element connected between each connection node of said plurality of seventh transistors and said first input terminal.

41. The shift register according to claim 38, further comprising

a diode connected between each connection node of said plurality of seventh transistors and said first input terminal such that said first input terminal serves as a cathode and said connection node serves as an anode.

42. The shift register according to claim 38, further comprising

an eighth transistor between each connection node of said plurality of seventh transistors and said first input terminal, having a control electrode connected to a second clock terminal receiving a second clock signal of different phase from said first clock signal.

43. A shift register comprising:

first and second input terminals, an output terminal and a clock terminal;

first and second voltage signal terminals respectively receiving first and second voltage signals complementary to each other;

a first transistor configured to supply a clock signal received at said clock terminal to said output terminal;

a second transistor configured to discharge said output terminal;

a first driving circuit configured to supply said first voltage signal to a first node to which a control electrode of said first transistor is connected, on the basis of a first input signal received at said first input terminal;

a second driving circuit configured to supply said second voltage signal to said first node, on the basis of a second input signal received at said second input terminal; and

an inverter with said first node serving as its input node and a second node connected to a control electrode of said second transistor serving as its output node, wherein

said first driving circuit includes a plurality of third transistors connected in series between said first node and said first voltage signal terminal and having control electrodes connected in common to said first input terminal, and

a second driving circuit includes a plurality of fourth transistors connected in series between said first node and said second voltage signal terminal and having control electrodes connected in common to said second input terminal.

44. The shift register according to claim 43, wherein

in the case where said first voltage signal is at an H (High) level higher than threshold voltages of said plurality of third and fourth transistors and said second voltage signal is at an L (Low) level lower than the threshold voltages of said plurality of third and fourth transistors, said first driving circuit is configured to turn on said plurality of third transistors when said first input signal reaches the H level, to thereby charge said first node, and then to pull down each connection node between said plurality of third transistors to the L level when the first input signal changes to the L level, and

in the case where said first voltage signal is at the L level and said second voltage signal is at the H level, said second driving circuit is configured to turn on said plurality of fourth transistors when said first input signal reaches the H level, to thereby charge said first node, and then to pull down each node between said plurality of fourth transistors to the L level when the second input signal changes to the L level.

45. The shift register according to claim 43, further comprising:

a first capacitive element connected between each connection node between said plurality of third transistors and said first input terminal; and

a second capacitive element connected between each connection node between said plurality of fourth transistors and said second input terminal.

46. The shift register according to claim 43, further comprising:

a first diode connected between each connection node between said plurality of third transistors and said first input terminal such that said first input terminal serves as a cathode and each connection node between said plurality of third transistors serves as an anode; and

a second diode connected between each connection node between said plurality of fourth transistors and said second input terminal such that said second input terminal serves as a cathode and each connection node between said plurality of fourth transistors serves as an anode.

47. The shift register according to claim 43, further comprising:

a fifth transistor between each connection node between said plurality of third transistors and said first input terminal, having a control electrode connected to said clock terminal; and

a sixth transistor between each connection node between said plurality of fourth transistors and said second input terminal, having a control electrode connected to said clock terminal.