METHOD FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE

• US 20080188056A1
• Filed: 12/28/2007
• Published: 08/07/2008
• Est. Priority Date: 02/06/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Gyu Hyun
• Granted Patent: US 7,846,809 B2
• Time in Patent Office: Days
• US Class Current: 438/386
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A method for forming a capacitor of a semiconductor device includes the steps of forming first and second sacrificial insulation layers over a semiconductor substrate divided into first and second regions. The second and first sacrificial insulation layers in the first region are etched to define in the first region of the semiconductor substrate. Storage nodes on surfaces of the holes are formed. A partial thickness of the second sacrificial insulation layer is etched to partially expose upper portions of the storage nodes. A mask pattern is formed to cover the first region while exposing the second sacrificial insulation layer remaining in the second region. The exposed second sacrificial insulation layer in the second region is removed to expose the first sacrificial insulation layer in the second region. The exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region is removed. The mask pattern is removed. The second sacrificial insulation layer remaining in the first region is removed.

Claims

1. A method for forming a capacitor of a semiconductor device, comprising the steps of:

forming a first sacrificial insulation layer and a second sacrificial insulation layer over a semiconductor substrate which is divided into a first region and a second region;

etching the second sacrificial insulation layer and the first sacrificial insulation layer in the first region to define holes in the first region of the semiconductor substrate;

forming storage nodes on surfaces of the holes;

etching a partial thickness of the second sacrificial insulation layer to partially expose upper portions of the storage nodes;

forming a mask pattern selectively covering the first region on the etched second sacrificial insulation layer, wherein the second sacrificial insulation layer remaining in the second region is not covered by the mask pattern;

removing the remained second sacrificial insulation layer in the second region to expose the first sacrificial insulation layer in the second region;

removing the exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region;

removing the mask pattern; and

removing the second sacrificial insulation layer remaining in the first region.

2. The method according to claim 1, wherein the first region is a cell region, and the second region is a peripheral region.

3. The method according to claim 1, wherein the first sacrificial insulation layer comprises any one of a PSG layer, an O₃-TEOS layer, an O₃-USG layer and an SOD layer.

4. The method according to claim 1, wherein the second sacrificial insulation layer comprises a PE-TEOS layer.

5. The method according to claim 1, wherein the storage nodes comprise at least one of a TiN layer, a W layer, and an Ru layer.

6. The method according to claim 1, wherein the step of etching the partial thickness of the second sacrificial insulation layer is implemented through a wet etching process.

7. The method according to claim 6, wherein the wet etching process is implemented using a mixed solution of NH₄F, HF, and H₂O.

8. The method according to claim 7, wherein, in the mixed solution, NH₄F, HF, and H₂O are mixed in a ratio in the range of 16˜

18;

1˜

2;

80˜

83.

9. The method according to claim 8, wherein, in the mixed solution, NH₄F, HF, and H₂O are mixed in the ratio of 17:

1.7;

81.3.

10. The method according to claim 1, wherein the mask pattern comprises a photoresist.

11. The method according to claim 1, wherein the step of removing the remained the second sacrificial insulation layer in the second region is implemented through a dry etching process.

12. The method according to claim 1, wherein the step of removing the exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region is implemented through a wet etching process.

13. The method according to claim 12, wherein the wet etching process is implemented using a mixed solution of NH₄F, HF, and H₂O.

14. The method according to claim 13, wherein, in the mixed solution, NH₄F, HF, and H₂O are mixed in a ratio in the range of 16˜

18;

1˜

2;

80˜

83.

15. The method according to claim 14, wherein, in the mixed solution, NH₄F, HF, and H₂O are mixed in the ratio of 17:

1.7;

81.3.

16. The method according to claim 1, wherein the step of removing the portion of the second sacrificial insulation layer remaining in the first region is implemented through an etching process using anhydrous HF gas.