INTERNAL BALANCED COIL FOR INDUCTIVELY COUPLED HIGH DENSITY PLASMA PROCESSING CHAMBER

• US 20080188090A1
• Filed: 02/02/2007
• Published: 08/07/2008
• Est. Priority Date: 02/02/2007
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Liang, Qiwei, Chen, Xinglong, Chen, Robert, Lubomirsky, Dmitry, Yieh, Ellie Y., Lai, Canfeng, Hua, Zhong Qiang, Rasheed, Muhammad, Lu, Siqing, Luo, Weiyi
• Application Number:
  US11/670,701
• Publication Number:
  US 20080188090A1
• Time in Patent Office: Days
• US Class Current: 438/778
• CPC Class Codes: C23C 16/507 using external electrodes, e.g. in tunnel type reactors
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma

Abstract

A coil is provided for use in a semiconductor processing system to generate a plasma with a magnetic field in a chamber. The coil comprises a first coil segment, a second coil segment and an internal balance capacitor. The first coils segment has a first end and a second end. The first end of the coil segment is adapted to connect to a power source. The second coil segment has a first and second end. The second end of the first coil segment is adapted to connect to an external balance capacitor. The internal balance capacitor is connected in series between the second end of the first coil segment and the first end of the second coil segment. The internal balance capacitor and the coil segments are adapted to provide a voltage peak along the first coil segment substantially aligned with a virtual ground along the second coil segment.

Claims

1. A substrate processing device, the device comprising:

a coil comprising a first coil segment and a second coil segment, the first and second coil segments arranged to generate a magnetic field, wherein the coil comprises at least about two turns;

at least one internal balance capacitor connected in series between the first coil segment and the second coil segment of the coil; and

a gas distributor disposed near the first coil, wherein an electric field extends from the coil through the gas distributor toward a grounded structure connected to the gas distributor, and wherein the at least one capacitor and segments of the coil are arranged to decrease a voltage of the electric field that extends from the coil through the gas distributor.

2. The device of claim 1 wherein the coil is adapted to provide a high power HDP/CVD process with a voltage below a chamber blackening threshold voltage.

3. The device of claim 1 wherein the two coil segments have substantially similar inductances.

4. The device of claim 1 wherein the coil comprises at least about 4 turns.

5. The device of claim 1 further comprising:

a second coil comprising a first coil segment and a second coil segment, the first and second coil segments of the second coil arranged to generate a second magnetic field; and

at least one internal balance capacitor connected in series between the first coil segment and the second coil segment of the second coil;

wherein the first coil and the second coil are arranged to at least partially overlap the magnetic fields to generate a plasma.

6. The device of claim 5 wherein the coils are adapted to provide a high power process with less than 1 kV applied to each coil.

7. The device of claim 5 wherein the coils are adapted to provide a high power process with less than about 750 V applied to each coil.

8. A method of depositing a layer on a substrate, the method comprising:

releasing a deposition gas from a gas distributor into a semiconductor process chamber;

generating a plasma with an induction coil that applies a magnetic field to the semiconductor process chamber;

charging a capacitor located between segments of the coil to decrease a voltage to the coil;

generating an electric field with the voltage to the coil, wherein the electric field extends from at least one of the coil segments through the gas distributor and toward a grounded structure; and

depositing the layer on the semiconductor substrate with the plasma.

9. The method of claim 8 wherein the electric field passes through a gas distributor comprising a baffle.

10. The method of claim 8 wherein the layer comprises a dielectric layer deposited with an HDP/CVD process.