PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES
First Claim
1. A processor comprising:
- a cache memory that comprises;
an array;
word lines; and
bit lines; and
a control module that accesses cells of said array during access cycles to access instructions stored in said cache memory,wherein said control module selectively performs one of a first sequential read and a first discrete read to access instructions in a first set of cells of said array that are connected to a first word line and that selectively performs one of a second sequential read and a second discrete read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line, andwherein said second word line is different than said first word line.
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Accused Products
Abstract
A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.
18 Citations
58 Claims
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1. A processor comprising:
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a cache memory that comprises; an array; word lines; and bit lines; and a control module that accesses cells of said array during access cycles to access instructions stored in said cache memory, wherein said control module selectively performs one of a first sequential read and a first discrete read to access instructions in a first set of cells of said array that are connected to a first word line and that selectively performs one of a second sequential read and a second discrete read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line, and wherein said second word line is different than said first word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 53, 54, 55)
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27. A method comprising:
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providing a cache memory that comprises; an array of cells; word lines; and bit lines; accessing cells of said array during access cycles to access instructions stored in said cache memory; performing one of a first discrete read and a first sequential read to access instructions in a first set of cells of said array that are connected to a first word line; and selectively performing one of a second discrete read and a second sequential read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line, wherein said second word line is different than said first word line. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 56, 57, 58)
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Specification