HDL Design Structure for Integrating Test Structures into an Integrated Circuit Design

• US 20080189671A1
• Filed: 04/21/2008
• Published: 08/07/2008
• Est. Priority Date: 07/24/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: McMahon, Robert, Habib, Nazmul, Perry, Troy
• Granted Patent: US 7,884,599 B2
• Time in Patent Office: Days
• US Class Current: 716/18
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The functional representations of selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected functional representations of test structures into the final layout of the design.

Claims

1. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a test structure, wherein said HDL design structure comprises:

an IC design comprising at least one device and at least one element;

a library comprising at least one device under test (DUT), wherein the at least one DUT matches the at least one device; and

a modified IC design comprising at least one control structure, the control structure coupled to the at least one DUT and the at least one element.

2. The HDL design structure of claim 1 further comprising:

a first list comprising a plurality of matching DUTs.

3. The HDL design structure of claim 2, further comprising:

a second list generated from the first list and a first database comprising priority specifications;

the second list comprising a plurality of prioritized matching DUTs.

4. The HDL design structure of claim 3, wherein the first database comprises at least one of a plurality of customer directives, a plurality of historical data, or a plurality of internal rules.

5. The HDL design structure of claim 3 further comprising:

at least one placement algorithm for placing at least one of the plurality of prioritized matching DUTs into the IC design.

6. The HDL design structure of claim 3 further comprising:

a third list comprising at least a portion of the plurality of prioritized matching DUTs corresponding to a plurality of elements,

the third list is generated from the second list and a second database comprising the plurality of elements, the elements corresponding to the IC design.

7. The HDL design structure of claim 6 further comprising a third database, the third database comprising at least a second portion prioritized matching DUTs which are not in the third list.

8. The HDL design structure of claim 1, wherein the HDL design structure comprises a netlist.

9. The HDL design structure of claim 1, wherein the HDL design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

10. The HDL design structure of claim 1, wherein the design structure resides in a programmable gate array.