Thin film transistors and methods of manufacturing the same

• US 20080191204A1
• Filed: 11/30/2007
• Published: 08/14/2008
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Park, Young-soo, Park, Jae-chul
• Granted Patent: US 8,143,678 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower layers. The upper layer may have a carrier concentration lower than the lower layer. A method of manufacturing a transistor may include: forming a channel layer on a substrate; forming source and drain electrodes on the substrate; forming a gate insulating layer on the substrate; and forming a gate electrode on the gate insulating layer above the channel layer. A method of manufacturing a transistor may include: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a channel layer on the gate insulating layer; and forming source and drain electrodes on the gate insulating layer.

Claims

1. A thin film transistor, comprising:

a gate insulting layer;

a gate electrode formed on a first side of the gate insulating layer;

a channel layer formed on a second side of the gate insulating layer;

a source electrode that contacts a first portion of the channel layer; and

a drain electrode that contacts a second portion of the channel layer;

wherein the channel layer has a double-layer structure, including an upper layer and a lower layer, and

wherein the upper layer has a carrier concentration lower than that of the lower layer.

2. The transistor of claim 1, wherein the channel layer is formed of a ZnO based material.

3. The transistor of claim 1, wherein the channel layer is formed of a(In₂O₃).b(Ga₂O₃).c(ZnO), where a, b, and c are real numbers such that a≧

0, b≧

0, and c>

0.

4. The transistor of claim 1, wherein the upper layer is doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.

5. The transistor of claim 4, wherein the carrier acceptor comprises one or more of Cu, Ag, Li, Na, K, Mg, Ca, Be, Au, Rg, Ni, Co, Rh, Pd, Ir, Pt, V, Nb, Ta, and N.

6. The transistor of claim 5, wherein the carrier acceptor comprises Cu, and Cu content of the upper layer is 29-44 atomic %.

7. The transistor of claim 6, wherein a thickness of the upper layer is 10-100 nm.

8. A method of manufacturing a thin film transistor, comprising:

forming a channel layer on a substrate;

forming a source electrode, that contacts a first portion of the channel layer, on the substrate;

forming a drain electrode, that contacts a second portion of the channel layer, on the substrate;

forming a gate insulating layer, that covers the channel layer, the source electrode, and the drain electrode, on the substrate; and

forming a gate electrode on the gate insulating layer above the channel layer;

wherein the channel layer has a double-layer structure, including an upper layer and a lower layer, and

wherein the upper layer has a carrier concentration lower than that of the lower layer.

9. The method of claim 8, wherein the channel layer is formed of a ZnO based material.

10. The method of claim 8, wherein the channel layer is formed in the double-layer structure by doping a carrier acceptor into an upper part of the channel layer.

11. The method of claim 10, wherein the carrier acceptor comprises one or more of Cu, Ag, Li, Na, K, Mg, Ca, Be, Au, Rg, Ni, Co, Rh, Pd, Ir, Pt, V, Nb, Ta, and N.

12. The method of claim 8, wherein the upper layer comprises a carrier acceptor, and

wherein the upper layer is formed using a sputtering method with a target doped with the carrier acceptor.

13. The method of claim 8, wherein the upper layer comprises a carrier acceptor,

wherein the upper layer is formed using a sputtering method or an evaporation method that uses or sputtering and evaporation methods that use at least two targets, and

wherein at least one of the targets is doped with the carrier acceptor.

14. The method of claim 13, wherein the carrier acceptor comprises Cu,

wherein the upper layer is formed using the sputtering method, and

wherein Cu content of the upper layer is 29-44 atomic %.

15. The method of claim 14, wherein the upper layer is formed to have a thickness of 10-100 nm.

16. The method of claim 8, wherein the upper layer comprises a carrier acceptor, and

wherein the upper layer is formed using a gas that comprises the carrier acceptor.

17. A method of manufacturing a thin film transistor, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer, that covers the gate electrode, on the substrate;

forming a channel layer on the gate insulating layer, above the gate electrode;

forming a source electrode, that contacts a first portion of the channel layer, on the gate insulating layer; and

forming a drain electrode, that contacts a second portion of the channel layer, on the gate insulating layer;

wherein the channel layer has a double-layer structure, including an upper layer and a lower layer, and

wherein the upper layer has a carrier concentration lower than that of the lower layer.

18. The method of claim 17, wherein the channel layer is formed of a ZnO based material.

19. The method of claim 17, wherein the channel layer is formed in the double-layer structure by doping a carrier acceptor into an upper part of the channel layer.

20. The method of claim 19, wherein the carrier acceptor comprises one or more of Cu, Ag, Li, Na, K, Mg, Ca, Be, Au, Rg, Ni, Co, Rh, Pd, Ir, Pt, V, Nb, Ta, and N.

21. The method of claim 17, wherein the upper layer comprises a carrier acceptor, and

wherein the upper layer is formed using a sputtering method with a target doped with the carrier acceptor.

22. The method of claim 17, wherein the upper layer comprises a carrier acceptor,

wherein the upper layer is formed using a sputtering method or an evaporation method that uses or sputtering and evaporation methods that use at least two targets, and

wherein at least one of the targets is doped with the carrier acceptor.

23. The method of claim 22, wherein the carrier acceptor comprises Cu,

wherein the upper layer is formed using the sputtering method, and

wherein Cu content of the upper layer is 29-44 atomic %.

24. The method of claim 23, wherein the upper layer is formed to have a thickness of 10-100 nm.25 The method of claim 17, wherein the upper layer comprises a carrier acceptor, and

wherein the upper layer is formed using a gas that comprises the carrier acceptor.