Scalable Power Field Effect Transistor with Improved Heavy Body Structure and Method of Manufacture

• US 20080191248A1
• Filed: 02/09/2007
• Published: 08/14/2008
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Wang, Qi, Sharp, Joelle, Huang, Ming-Huang
• Granted Patent: US 7,564,096 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

Claims

1. A field effect transistor (FET) comprising:

a semiconductor region of a first conductivity type;

a well region of a second conductivity type extending over the semiconductor region;

a gate electrode adjacent to but insulated from the well region;

a source region of the first conductivity type in the well region;

a heavy body recess extending into and terminating within the well region adjacent the source region; and

a heavy body material having a lower energy gap than the well region at least partially filling the heavy body recess.

2. The FET of claim 1 wherein the heavy body material comprises silicon germanium.

3. The FET of claim 1 wherein the heavy body material comprises boron doped silicon germanium.

4. The FET of claim 3 wherein the boron concentration is greater than 5×

10¹⁸ cm<sup>−

3</sup>.

5. The FET of claim 1 wherein the heavy body material comprises poly silicon germanium.

6. The FET of claim 1 wherein the heavy body material comprises epitaxial silicon germanium.

7. The FET of claim 1 wherein the heavy body material comprises Si_1-xGe_x where x>

0.1.

8. The FET of claim 1 wherein the heavy body material comprises greater than or equal to about 10 percent germanium mole fraction.

9. The FET of claim 1 wherein the heavy body recess is substantially V-shaped, and the heavy body material comprises SiGe wherein a concentration of germanium in the SiGe decreases in a direction from the walls of the V-shaped heavy body recess toward a center of the heavy body recess.

10. The FET of claim 1 wherein a top surface of the heavy body material is below a top surface of the source region so that the heavy body material and the source region do not overlap.

11. The FET of claim 1 wherein the gate electrode is disposed in a trench extending into the well region and terminating in the semiconductor region.

12. The FET of claim 11 wherein a top surface of the heavy body material is substantially coplanar with a top surface of the source region.

13. The FET of claim 12 further comprising:

a dielectric dome extending over the gate electrode and overlapping the source region; and

an interconnect layer contacting the source region and the heavy body material, wherein the dielectric dome insulates the gate electrode from the interconnect layer.

14. The FET of claim 12 further comprising:

a dielectric cap filling an upper portion of the trench over the gate electrode, the dielectric cap having a top surface substantially coplanar with a top surface of the source region; and

an interconnect layer contacting the source region and the heavy body material, wherein the dielectric cap insulates the gate electrode from the interconnect layer.

15. The FET of claim 11 wherein the trench further includes:

a thick bottom dielectric filling a bottom portion of the trench beneath the gate electrode; and

a gate dielectric lining the trench sidewalls, the gate dielectric being thinner than the thick bottom dielectric.

16. The FET of claim 11 wherein the trench further includes:

a shield electrode filling a lower portion of the trench beneath the gate electrode, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric layer extending between the shield electrode and the gate electrode; and

a gate dielectric extending along upper trench sidewalls, the gate dielectric being thinner than the shield dielectric.

17. The FET of claim 1 wherein the gate electrode laterally extends over but is insulted from the well region by a layer of gate dielectric.

18. A field effect transistor (FET) comprising:

a semiconductor region of a first conductivity type;

a well region of a second conductivity type extending over the semiconductor region;

a gate electrode adjacent to but insulated from the well region;

a source region of the first conductivity type in the well region;

a heavy body recess extending into and terminating within the well region adjacent the source region; and

a heavy body region extending in the well region along a bottom of the heavy body recess, wherein the heavy body region comprises a material having a lower energy gap than that of the well region.

19. The FET of claim 18 further comprising an interconnect layer substantially filling the heavy body recess so as to electrically contact the heavy body region and the source region.

20. The FET of claim 18 wherein the heavy body region comprises silicon germanium.

21. The FET of claim 18 wherein the heavy body region comprises a boron doped silicon germanium.

22. The FET of claim 18 wherein the heavy body region comprises Si_1-xGe_x where x>

0.1.

23. The FET of claim 18 wherein the heavy body region comprises greater than or equal to about 10 percent germanium mole fraction.

24. The FET of claim 18 wherein the gate electrode is disposed in a trench extending into the well region and terminating in the semiconductor region.

25. The FET of claim 24 further comprising:

a dielectric cap filling an upper portion of the trench over the gate electrode, the dielectric cap having a top surface substantially coplanar with a top surface of the source region; and

an interconnect layer contacting the source region and the heavy body region, wherein the dielectric cap insulates the gate electrode from the interconnect layer.

26. The FET of claim 24 wherein the trench further includes:

a thick bottom dielectric filling a bottom portion of the trench beneath the gate electrode; and

a gate dielectric lining the trench sidewalls, the gate dielectric being thinner than the thick bottom dielectric.

27. The FET of claim 24 wherein the trench further includes:

a shield dielectric lining lower sidewalls and bottom of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric layer extending between the shield electrode and the gate electrode; and

a gate dielectric extending along upper trench sidewalls, the gate dielectric being thinner than the shield dielectric.

28. The FET of claim 18 wherein the gate electrode laterally extends over but is insulted from the well region by a layer of gate dielectric.

29. A field effect transistor (FET) comprising:

a semiconductor region of a first conductivity type;

a well region of a second conductivity type extending over the semiconductor region;

a gate electrode adjacent to but insulated from the well region;

a source region of the first conductivity type in the well region;

a heavy body region in electrical contact with the well region, comprising a material having a lower energy gap than the well region.

30. The FET of claim 29 wherein the heavy body region comprises silicon germanium.

31. The FET of claim 29 wherein the heavy body region comprises boron doped silicon germanium.

32. The FET of claim 29 wherein the heavy body region comprises Si_1-xGe_x where x>

0.1.

33. The FET of claim 29 wherein the gate electrode is disposed in a trench extending into the well region and terminating in the semiconductor region.

34. The FET of claim 33 wherein the trench further includes:

a thick bottom dielectric filling a bottom portion of the trench beneath the gate electrode; and

a gate dielectric lining the trench sidewalls, the gate dielectric being thinner than the thick bottom dielectric.

35. The FET of claim 33 wherein the trench further includes:

a shield electrode filling a lower portion of the trench beneath the gate electrode, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric layer extending between the shield electrode and the gate electrode; and

a gate dielectric extending along upper trench sidewalls, the gate dielectric being thinner than the shield dielectric.

36. The FET of claim 29 wherein the gate electrode laterally extends over but is insulted from the well region by a layer of gate dielectric.

37. The FET of claim 29 further comprising:

a heavy body recess extending into and terminating within the well region adjacent the source region, the heavy body region extending along a bottom of the heavy body recess; and

an interconnect layer extending into the heavy body recess to electrically contact the heavy body region and the source region.

38. The FET of claim 29 further comprising a heavy body recess extending into and terminating within the well region adjacent the source region, wherein the heavy body region at least partially fills the heavy body recess.

39-73. -73. (canceled)