Non-volatile memory devices and methods of operating and fabricating the same

• US 20080191264A1
• Filed: 01/22/2008
• Published: 08/14/2008
• Est. Priority Date: 01/24/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Park, Yoon-dong, Lee, Tae-hee, Kim, Suk-pil, Kim, Won-Joo, Koo, June-mo
• Application Number:
  US12/010,139
• Publication Number:
  US 20080191264A1
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

Claims

1. A non-volatile memory device, comprising:

one or more oxide based compound semiconductor layers;

a plurality of auxiliary gate electrodes insulated from the one or more oxide based compound semiconductor layers;

a plurality of control gate electrodes respectively positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes, the plurality of control gate electrodes being insulated from the one or more oxide based compound semiconductor layers; and

a plurality of charge storing layers respectively between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

2. The non-volatile memory device of claim 1, wherein the one or more oxide based compound semiconductor layers includes a plurality of oxide based compound semiconductor layers separately positioned in strings.

3. The non-volatile memory device of claim 1, further comprising:

an isolation layer between the plurality of oxide based compound semiconductor layers.

4. The non-volatile memory device of claim 1, further comprising:

a substrate electrode under the bottom surfaces of the plurality of oxide based compound semiconductor layers.

5. The non-volatile memory device of claim 1, wherein the plurality of oxide based compound semiconductor layers are divided into a plurality of blocks, and a plurality of substrate electrodes are further formed to be in contact with the blocks of the plurality of oxide based compound semiconductor layers, respectively.

6. The non-volatile memory device of claim 1, wherein the plurality of control gate electrodes are formed on top surfaces of the one or more oxide based compound semiconductor layers, and the plurality of auxiliary gate electrodes are formed to be recessed into the one or more oxide based compound semiconductor layers.

7. The non-volatile memory device of claim 6, further comprising:

a first channel region near surfaces of the one or more oxide based compound semiconductor layers surrounding the plurality of auxiliary gate electrodes; and

a second channel region near surfaces of the one or more oxide based compound semiconductor layers below the plurality of control gate electrodes,

wherein the first and second channel regions are connected to each other.

8. The non-volatile memory device of claim 6, further comprising:

a plurality of capping insulating layers respectively on the plurality of auxiliary gate electrodes.

9. The non-volatile memory device of claim 1, wherein the plurality of control gate electrodes are formed to be recessed into the one or more oxide based compound semiconductor layers, and the plurality of auxiliary gate electrodes are formed on the top surfaces of the one or more oxide based compound semiconductor layers.

10. The non-volatile memory device of claim 9, further comprising:

a plurality of capping insulating layers respectively on the plurality of control gate electrodes.

11. The non-volatile memory device of claim 9, further comprising:

a first channel region near surfaces of the one or more oxide based compound semiconductor layers below the plurality of auxiliary gate electrodes; and

a second channel region near surfaces of the one or more oxide based compound semiconductor layers surrounding the plurality of control gate electrodes,

wherein the first and second channel regions are connected to each other.

12. The non-volatile memory device of claim 1, further comprising:

a plurality of tunneling insulating layers respectively between the one or more oxide based compound semiconductor layers and the plurality of charge storing layers; and

a plurality of blocking insulating layers respectively between the plurality of charge storing layers and the plurality of control gate electrodes.

13. The non-volatile memory device of claim 1, further comprising:

a plurality of gate insulating layers respectively between the one or more oxide based compound semiconductor layers and the plurality of auxiliary gate electrodes.

14. The non-volatile memory device of claim 1, wherein the oxide based compound semiconductor layer comprises ZnO.

15. A method of operating the non-volatile memory device of claim 1, comprising:

a program operation for storing data in a first charge storing layer selected from among the plurality of charge storing layers; and

a read operation for reading a data state of a second charge storing layer selected from among the plurality of charge storing layers,

wherein a first pass voltage is applied to the plurality of auxiliary gate electrodes in the program and read operations.

16. The method of claim 15, wherein, in the program operation, a program voltage is applied to a first control gate electrode positioned on the selected first charge storing layer, the first control gate electrode being from among the plurality of control gate electrodes, and further wherein, a second pass voltage is applied to the other control gate electrodes.

17. The method of claim 15, wherein in the read operation, a read voltage is applied to a second control gate electrode positioned on the selected second charge storing layer, the second control gate electrode being from among the plurality of control gate electrodes, and further wherein, a second pass voltage is applied to the other control gate electrodes.

18. The method of claim 15, further comprising:

an erase operation simultaneously erasing data stored in the plurality of charge storing layers.

19. The method of claim 15, further comprising:

an erase operation dividing the plurality of charge storing layers into a plurality of blocks and simultaneously erasing data of a first block selected from among the plurality of blocks.

20. The method of claim 19, wherein the program or read operation is performed with respect to a second block selected from among the plurality of blocks while simultaneously erasing the data of the first block.

21. A method of fabricating a non-volatile memory device, comprising:

providing one or more oxide based compound semiconductor layers;

forming a plurality of auxiliary gate electrodes to be insulated from the one or more oxide based compound semiconductor layers;

forming a plurality of control gate electrodes to be respectively positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes, the plurality of control gate electrodes being insulated from the one or more oxide based compound semiconductor layers; and

forming a plurality of charge storing layers respectively between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

22. The method of claim 21, wherein the providing of the one or more oxide based compound semiconductor layers includes providing a plurality of oxide based compound semiconductor layers separately positioned in strings.

23. The method of claim 21, further comprising:

forming an isolation layer between the plurality of oxide based compound semiconductor layers before forming the plurality of auxiliary gate electrodes.

24. The method of claim 21, wherein the plurality of oxide based compound semiconductor layers are formed on a substrate electrode.

25. The method of claim 21, wherein the plurality of oxide based compound semiconductor layers are formed as a plurality of blocks on a plurality of substrate electrodes.

26. The method of claim 21, wherein the plurality of control gate electrodes are formed on top surfaces of the one or more oxide based compound semiconductor layers, and the plurality of auxiliary gate electrodes are formed to be recessed into the one or more oxide based compound semiconductor layers.

27. The method of claim 21, wherein the plurality of control gate electrodes are formed to be recessed into the one or more oxide based compound semiconductor layers, and the plurality of auxiliary gate electrodes are formed on the top surfaces of the one or more oxide based compound semiconductor layers.

28-34. -34. (canceled)