SEMICONDUCTOR CIRCUIT

• US 20080191312A1
• Filed: 02/29/2008
• Published: 08/14/2008
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun, Oh, ChoonSik
• Granted Patent: US 7,800,199 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01038 Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01056 Barium [Ba]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.

Claims

1. A method of forming a semiconductor circuit, comprising:

providing a carrier substrate which carries an interconnect region;

providing a donor layer coupled to a donor substrate with a detach layer;

coupling the donor layer to the carrier substrate through the interconnect region;

decoupling the donor substrate from the detach layer so the donor layer is carried by the carrier substrate; and

forming an electronic device with the donor layer.

2. The method of claim 1, wherein the interconnect region includes a refractory metal.

3. The method of claim 1, wherein the electronic device is formed with the donor layer after the donor layer is coupled to the carrier substrate.

4. The method of claim 1, wherein the step of coupling a donor layer to the substrate includes forming a bonding interface.

5. The method of claim 1, wherein the donor layer consists essentially of a semiconductor material before the donor layer is coupled to the carrier substrate.

6. The method of claim 1, further including forming a capacitor connected to the electronic device.

7. The method of claim 6, wherein the capacitor is formed after the donor layer is coupled to the substrate.

8. The method of claim 1, wherein the electronic device operates as a static random access memory device.

9. The method of claim 1, wherein the electronic device operates as a non-volatile memory device.

10. The method of claim 1, wherein the detach layer includes porous semiconductor material.

11. The method of claim 1, wherein the detach layer includes dielectric material.

12. A method of forming a semiconductor circuit, comprising:

providing a carrier substrate which carries an interconnect region;

providing a donor layer coupled to a donor substrate with a detach layer;

coupling the donor layer to the carrier substrate by forming a bonding interface;

decoupling the donor substrate from the detach layer so the donor substrate is carried by the carrier substrate; and

forming a first electronic device with the donor layer after the bonding interface is formed.

13. The method of claim 12, wherein the donor layer does not include a second electronic device before the bonding interface is formed.

14. The method of claim 12, wherein the donor layer consists essentially of a semiconductor material before the bonding interface is formed.

15. The method of claim 12, wherein a portion of the donor layer between the electronic device and bonding interface consists essentially of semiconductor material.

16. The method of claim 12, further including forming a capacitor connected to the electronic device.

17. The method of claim 16, wherein the capacitor is formed after the bonding interface.

18. The method of claim 16, wherein the electronic device and capacitor operate as a dynamic random access memory cell.

19. The method of claim 12, wherein the electronic device operates as a static random access memory device.

20. The method of claim 12, wherein the electronic device operates as a non-volatile memory device.

21. The method of claim 12, wherein the detach layer includes porous semiconductor material.

22. The method of claim 12, wherein the detach layer includes dielectric material.

23. A semiconductor circuit, comprising:

a carrier substrate which carries an interconnect region;

a donor layer coupled to the interconnect region through a bonding interface; and

an electronic device formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed;

wherein the portion of the donor layer between the electronic device and interconnect region consists essentially of semiconductor material.

24. The circuit of claim 23, wherein the interconnect region includes a refractory metal.

25. The circuit of claim 23, wherein the electronic device is positioned away from the bonding interface.

26. The circuit of claim 23, wherein the electronic device is a horizontally oriented device or vertically oriented device.

27. The circuit of claim 23, further including a capacitor connected to the electronic device.

28. The circuit of claim 27, wherein the capacitor is formed after the bonding interface is formed.

29. The circuit of claim 23, wherein the electronic device operates as a static random access memory device.

30. The circuit of claim 23, wherein the electronic device operates as a non-volatile memory device.

31. The circuit of claim 23, wherein the detach layer includes porous semiconductor material.

32. The circuit of claim 23, wherein the detach layer includes dielectric material.