ISOLATION BUFFERS WITH CONTROLLED EQUAL TIME DELAYS

• US 20080191722A1
• Filed: 04/22/2008
• Published: 08/14/2008
• Est. Priority Date: 10/23/2003
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Granted Patent: US 7,586,300 B2
• Time in Patent Office: Days
• US Class Current: 324/762.05
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/265 with adjustable delay

Abstract

A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffet to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.

Claims

1-13. -13. (canceled)

14. A test system comprising:

a tester having test channels for transmitting and receiving test signals for testing devices on a wafer;

isolation buffers having inputs connected in common to one of the tester channels, each one of the isolation buffers further having an output; and

probes each configured to contact one of the devices on the wafer, and each of the probes further having a terminal connected to the output of one of the isolation buffers.

15. The test system of claim 14, wherein each of the isolation buffers further has a variable delay control input for receiving a variable voltage potential set to control a time delay of a signal between the input and output of the respective isolation buffer, the test system further comprising:

a delay control circuit having an output connected to the variable delay control input of the isolation buffers, the delay control circuit setting a magnitude of a control voltage potential at its output based on a time delay reference.

16. The test system of claim 15, further comprising:

driver buffers each connecting the output of one of the isolation buffers to one of the probes, and each having a power supply input connected to receive the system voltage.

17. The apparatus of claim 15, wherein the delay control circuit comprises:

an oscillator;

a reference delay line providing the time delay reference, the reference delay line having an input connected to the oscillator, and having an output;

a reference buffer having a signal input connected to the oscillator, a variable delay control input, and having an output; and

a phase comparator having a first input connected to the output of the reference delay line and a second input connected to the output of the reference buffer, and having an output connected to the variable delay control inputs of the reference buffer and the isolation buffers.

18. The test system of claim 14, wherein each of the isolation buffers has a power supply input connected to receive the system power supply voltage, the test system further comprising:

a variable delay control buffer connecting the inputs of the isolation buffers to the tester, the variable delay control buffer further having a variable delay control input; and

a delay control circuit having an output connected to the variable delay control input of the variable delay control buffer, the delay control circuit setting a delay control voltage potential at its output based on a time delay reference.

19. (canceled)

20. A method of testing integrated circuits on a wafer comprising:

supplying test data signals from a tester to be distributed from a tester channel to one of a plurality of probes configured to connect to test pads on an integrated circuit (IC); and

distributing the channel through isolation buffers to multiple branches, each branch being connected to one of the plurality of probes; and

controlling delay through the isolation buffers so that each isolation buffer provides substantially the same delay.

21. The method of claim 20, wherein the step of controlling delay through the isolation buffers controls delay by varying a power supply voltage applied to the isolation buffers.

22. The method of claim 20, wherein the step of controlling delay through the isolation buffers controls delay by varying current through the isolation buffers.

23. The method of claim 20, further comprising:

providing a variable delay buffer in the channel prior to the multiple branches; and

controlling delay of the variable delay buffer to provide substantially the same delay through the each of the multiple branches.