Accessing multiple user states concurrently in a configurable IC

• US 20080191735A1
• Filed: 03/13/2006
• Published: 08/14/2008
• Est. Priority Date: 07/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Khubchandani, Teju, Hutchings, Brad, Schmit, Herman, Redgrave, Jason
• Granted Patent: US 7,788,478 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes configurable resources (e.g., configurable logic resources, routing resources, memory resources, etc.) that can be grouped in conceptual configurable tiles that are arranged in several rows and columns. Some embodiments allow tiles to be individually addressed, globally addressed (i.e., all addressed together), or addressed based on their tile types. The configurable IC includes numerous user-design state elements (“UDS elements”) in some embodiments. In some embodiments, the configuration/debug network has a streaming mode that can direct various circuits in one or more configurable tiles to stream out their data during the operation of the configurable IC. Accordingly, in the embodiments where the configuration/debug network connects to some or all of the UDS elements, the configurable/debug network can be used in a streaming mode to stream out data from the UDS elements of the tiles, in order to identify any errors in the operation of the IC. In other words, the streaming of the data from the UDS elements can be used to debug the operation of the configurable IC. In some embodiments, the configuration/debug network has a broadcasting mode that can direct various resources (e.g., memories, storage elements, etc.) in one or more configurable tiles to store the same data. For instance, the broadcasting mode can be used to initialize the memory blocks in the configurable memory tiles.

Claims

1. A method of accessing a configurable integrated circuit (IC) having a plurality of user design state (“

UDS”

) circuits, the method comprising;

a) addressing a plurality of the UDS circuits concurrently while the IC is performing user-design operations;

b) after addressing the plurality of the UDS circuits, concurrently reading state values stored by the addressed UDS circuits at at least the user-design operating frequency.

2. The method of claim 1,

wherein the configurable IC includes a debug network;

wherein addressing the plurality of UDS circuits comprises transmitting at least one address for the plurality of UDS circuits over the debug network of the configurable IC.

3. The method of claim 2, wherein the transmitted address specifies a type of circuits in the configurable IC.

4. The method of claim 1,

wherein the configurable IC includes a debug network;

wherein reading the plurality of UDS circuits comprises transmitting at least one read instruction over the debug network of the configurable IC.

5. The method of claim 1,

wherein the configurable IC includes a debug network,

wherein the reading comprises reading the state values onto the debug network.

6. The method of claim 5 further comprising:

defining merge values for specifying how state values from two different UDS circuits should merge onto a shared resource of the debug network.

7. The method of claim 6, wherein the shared resource of the debug network is a bus line of the debug network.

8. The method of claim 7, wherein the bus line is a vertical column line.

9. The method of claim 7, wherein the bus line is a horizontal row line.

10. The method of claim 6 further comprising:

outputting the read and merged state values from the IC through the debug network.

11. The method of claim 1, wherein the reading includes concurrently reading state values stored by the addressed UDS circuits in a plurality of successive clock cycles during the user-design operation of the IC.

12. A configurable integrated circuit (IC) comprising:

a plurality of user design state (UDS) circuits;

a debug network communicatively coupled to the UDS circuits,

said debug network for addressing concurrently a plurality of the UDS circuits while the IC is performing user-design operations;

said debug network further for reading concurrently state values stored by the addressed UDS circuits at at least the user-design operating frequency.

13. The configurable IC of claim 12,

wherein to address the plurality of UDS circuits, at least one address is transmitted for the plurality of UDS circuits is transmitted over the debug network of the configurable IC.

14. The configurable IC of claim 13, wherein the transmitted address specifies a type of circuits in the configurable IC.

15. The configurable IC of claim 12,

wherein to read the plurality of UDS circuits, at least one read instruction is transmitted over the debug network of the configurable IC.

16. The configurable IC of claim 12,

wherein to read the plurality of UDS circuits, the read state values are read onto the debug network.

17. The configurable IC of claim 16, wherein the debug network comprises:

merging circuits for specifying how state values from different UDS circuits should merge onto shared resources of the debug network.

18. The configurable IC of claim 17, wherein the shared resource of the debug network is a bus line of the debug network.

19. The configurable IC of claim 17,

wherein the debug network further comprises intersecting bus lines;

wherein the merging circuits comprise;

masking circuits for specifying how state values from different UDS circuits connected to the same set of lines should merge onto the same set of lines;

intersect-merge circuits for specifying how state values carried on two sets of intersecting lines should merge.

20. The configurable IC of claim 19, wherein the intersecting bus lines are vertical and horizontal lines.

21. The configurable IC of claim 12, wherein the debug network reads concurrently state values in a plurality of successive clock cycles during the user-design operation of the IC.

22. A method of accessing a configurable integrated circuit (IC) having a plurality of circuits, the method comprising:

a) addressing a plurality of the circuits concurrently;

b) after addressing the plurality of the UDS circuits, writing at least one common value to the addressed circuits concurrently.

23. The method of claim 22,

wherein the configurable IC includes a configuration network;

wherein addressing the plurality of circuits comprises transmitting at least one address for the plurality of circuits over the debug network of the configurable IC.

24. The method of claim 23, wherein the transmitted address specifies a type of circuits in the configurable IC.

25. The method of claim 22,

wherein the configurable IC includes a debug network;

wherein writing to the plurality of circuits comprises transmitting at least one write instruction over the debug network of the configurable IC.

26. The method of claim 22,

wherein the configurable IC includes a debug network,

wherein the reading comprises reading the state values onto the debug network.