Method and apparatus for universal program controlled bus architecture

• US 20080191739A1
• Filed: 04/15/2008
• Published: 08/14/2008
• Est. Priority Date: 09/04/1996
• Status: Abandoned Application

• Current Assignee: Benjamin S. Ting, Peter M. Pani
• Original Assignee: Benjamin S. Ting, Peter M. Pani
• Inventors: Ting, Benjamin S., Pani, Peter M.
• Application Number:
  US12/148,071
• Publication Number:
  US 20080191739A1
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

Claims

1. An integrated circuit, comprising:

a programmable logic array comprising;

a plurality of logic cells; and

programmable interconnections to receive digital input signals and to perform logical functions to transmit digital output signals;

a megacell comprising a plurality of functional blocks receiving digital inputs and transmitting digital outputs, wherein the megacell does not exclusively perform a memory function; and

a programmable interconnections subsystem to provide communication between the programmable logic array and the megacell.

2. The integrated circuit as set forth in claim 1, wherein the megacell is implemented using programmed metal masks.

3. The integrated circuit as set forth in claim 1, wherein the megacell is implemented using customized masks.

4. A method, comprising:

performing a processing function by a megacell; and

communicating digital signals between the megacell and a programmable logic array using a programmable interconnection subsystem.

5. The method of claim 4, further comprising selecting, within the programmable interconnection subsystem, one of the digital signals using tri-statable logic control for at least one of input to or output from the megacell.

6. The method of claim 4, further comprising selecting, within the programmable interconnection subsystem, one of the digital signals using tri-statable logic control for at least one of input to or output from the programmable logic array.

7. The method of claim 4, further comprising programming the programmable interconnection subsystem to enable the communicating of the digital signals.

8. The method of claim 6, further comprising providing a tri-state to the logic control in the programmable interconnection subsystem to enable the communicating.