HIGH-SPEED DIFFERENTIAL RECEIVER

• US 20080191745A1
• Filed: 04/21/2008
• Published: 08/14/2008
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Devon Glenford, Lawson, William Frederick
• Granted Patent: US 7,482,838 B2
• Time in Patent Office: Days
• US Class Current: 326/83
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.

Claims

1-11. -11. (canceled)

12. A high-speed differential receiver used between a high voltage domain and a low voltage domain;

said high-speed differential receiver comprising;

a wide common mode differential amplifier receiving differential input signals and providing amplified differential output signals;

a differential level shifter coupled to said wide common mode differential amplifier for providing voltage level shifted differential signals;

said wide common mode differential amplifier and differential level shifter operating at the high voltage domain;

said differential level shifter including a first pair of first P-channel field effect transistors (PFETs) connected to the high voltage domain supply, each said first PFET of said first pair of PFETs being connected to the wide common mode differential amplifier and respectively receives a gate input of a respective one of said amplified differential output signals, each said first PFET connected in series with a respective first N-channel field effect transistor (NFET) between the high voltage domain supply and ground, and a gate of each said first NFET is cross connected to a common drain connection of the other series connected first PFET and first NFET; and

a common drain connection of each said first PFET and said respective first NFET respectively providing a drain output of a respective one of said voltage level shifted differential signals;

a biased differential amplifier operating at the low voltage domain and coupled to said differential level shifter receiving said voltage level shifted differential signals and an enable signal for providing a biased output signal;

said biased differential amplifier including a second pair of second P-channel field effect transistors (PFETs) connected to the low voltage domain supply;

each said second PFET of said second pair of PFETs having a gate input enabled responsive to said enable signal and each said second PFET of said second pair of PFETs being series connected with a respective second N-channel field effect transistor (NFET) between the low voltage domain supply and a voltage bias node;

said biased differential amplifier including a series-connected pair of third N-channel field effect transistors (NFETs) connected in series between said voltage bias node and ground; and

a transistor stack including a series-connected third P-channel field effect transistor (PFET) and a fourth N-channel field effect transistors (NFET) and a parallel-connected pair of a fifth N-channel field effect transistor (NFET) and a sixth N-channel field effect transistor (NFET) connected in series between the low voltage domain supply and ground;

said third P-channel field effect transistor (PFET) and said sixth N-channel field effect transistor (NFET) respectively receiving a gate input of an inverted enable signal; and

said third N-channel field effect transistors (NFETs) respectively receiving a gate input of a source and drain connection of the series-connected third P-channel field effect transistor (PFET) and fourth N-channel field effect transistors (NFET) and of a source and drain connection of the series-connected fourth N-channel field effect transistors (NFET) and said fifth N-channel field effect transistors (NFET);

said respective second NFET having a gate connected to said respective common drain connection of each said first PFET and said respective first NFET of said differential level shifter; and

a common drain connection of one of said second PFET; and

said respective second NFET of said biased differential amplifier providing the biased output signal responsive to said enable signal.

14. A high-speed differential receiver as recited in claim 12 wherein the high voltage domain includes a range between 2.3 Volts and 2.7 Volts.

15. A high-speed differential receiver as recited in claim 12 wherein the low voltage domain includes a range between 0.8 Volts and 1.3 Volts.

16. A high-speed differential receiver as recited in claim 12 includes a NAND INVERT output stage coupled to said biased differential amplifier.

17. A high-speed differential receiver as recited in claim 12 includes a terminator connected between a pair of inputs of said wide common mode differential amplifier receiving said differential input signals.

13. (canceled)