Imaging device

• US 20080192132A1
• Filed: 12/06/2007
• Published: 08/14/2008
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: HL Klemove Corporation
• Original Assignee: Gentex Corporation
• Inventors: Andrus, Jeremy C., Bechtel, Jon H.
• Granted Patent: US 8,289,430 B2
• Time in Patent Office: Days
• US Class Current: 348/294
• CPC Class Codes: B60R 2001/1215 with information displays
• CPC Class Codes: B60R 2001/1253 with cameras, video cameras or video screens
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

The present invention relates to improved imaging devices having high dynamic range and to monitoring and automatic control systems incorporating the improved imaging devices.

Claims

1. An imaging device, comprising:

an array of pixels wherein each active pixel of said array of pixels is individually subjected to a series of tasks comprising;

selection and initiation of an available integration period for a given pixel and recording of an indication of an integration period initiated for said given pixel;

taking a single digitized reading of an integrated charge on said given pixel using a selected integration period at a site which is at least partially outside of said array of pixels and output of a signal representing a light level reading for said given pixel based on said digitized reading and said selected integration period.

2. An imaging device as in claim 1 wherein a pixel reset task is used to initiate a selectable integration period.

3. An imaging device as in claim 1 wherein the execution of tasks to select an integration period for a given pixel is confined to a period during which the longest integration may take place for said pixel.

4. An imaging device as in claim 1 wherein a parallel addressable group of pixels constitutes a substantial portion of a row of pixels in said array of pixels.

5. An imaging device as in claim 1 wherein ratios of one or more available integration periods to the next shorter integration period is approximately an integral power of 2, said integral power being greater than 1.

6. An imaging device as in claim 1 wherein four or fewer bits of data are stored for each pixel in memory.

7. An imaging device as in claim 6 wherein said memory is fabricated on a same integrated circuit substrate as the said array of pixels.

8. An imaging device as in claim 1 wherein only one digitized reading of an integrated charge level is taken for each pixel and digitized readings are taken for pixels in a predetermined order.

9. An imaging device as in claim 1 wherein different sets of selectable integration periods are provided for different image acquisition sequences.

10. An imaging device as in claim 9 wherein a first of said set of selectable integration periods is utilized in ambient lighting conditions above a threshold and a second of said set of selectable integration periods is utilized in ambient light conditions below a threshold.

11. An imaging device as in claim 1 wherein all of the integration periods which may be selected for a pixel end at the same time.

12. An imaging device as in claim 2 wherein the determination to reset a given pixel to initiate a shorter integration period is based at least in part on a result of a compare task of an indication of the accumulated charge on said given pixel to a threshold level after partial integration.

13. An imaging device as in claim 12 wherein compare task is analog and is performed at at least one location generally external to said array of pixels.

14. An imaging device as in claim 2 wherein reset to begin a shorter integration period is bypassed for a pixel if a recorded indication of an active integration period for said pixel indicates that said pixel was not reset during an immediately prior conditional reset task for said pixel.

15. An imaging device as in claim 6 wherein dynamic memory is used for memory associated with each pixel.

16. An imaging device as in claim 15 wherein said dynamic memory incorporates capacitive elements to store a bit value.

17. An imaging device as in claim 15 wherein refresh tasks for said dynamic memory is scheduled along with other image acquisition tasks.

18. An imaging device as in claim 1 wherein readout of parallel addressable groups of pixels is performed at periodic intervals during an image acquisition sequence.

19. An imaging device as in claim 1 wherein a ratio of a longest to a shortest available integration period is greater than 3500.

20. An imaging device as in claim 1 wherein a ratio of any available integration period other than a shortest to a next shorter available integration period is less than 10.

21. An imaging device in claim 1 wherein said available integration periods decrease ratio-metrically.

22. An imaging device in claim 1 wherein said available integration periods decrease geometrically.

23. An imaging device, comprising:

an array of pixels partitioned into at least 16 parallel addressable groups of pixels configured such that any given parallel addressable group of pixels within said array of pixels may be independently selected and subject active pixels of said selected parallel addressable group of pixels to at least one specified task, wherein at least one of task is a selective reset task performed as a single task simultaneously operating on at least a substantial subset of active pixels of said selected parallel addressable group of pixels to determine active pixels to selectively reset and to perform said reset selectively according to a determination and recordation of an indication of a reset for each pixel which is reset, said tasks being performed in parallel for at least a substantial subset of pixels in said selected parallel addressable group of pixels.

24. An imaging device as in claim 23 wherein a said parallel addressable group of pixels defines a substantial portion of a row of pixels in said array of pixels.

25. An imaging device as in claim 23 wherein a group of commonly spectral filtered pixels of a series of Bayer patterned spectrally filter pixels defines a parallel addressable group of pixels.

26. An imaging device as in claim 24 further comprising a row of reset control circuits wherein each is linked via an associated communication path to an individual pixel in said selected parallel addressable group of pixels.

27. An imaging device as in claim 26 wherein said row of reset control circuits is configured to perform selective reset of pixels in said selected parallel addressable group of pixels in a substantially parallel operation.

28. An imaging device as in claim 23 wherein comparators and logic circuits perform selective reset functions and are partitioned into similar blocks each of which operate on one or more pixels of said selected parallel addressable group of pixels with the logic in the blocks at least partially duplicated from one block to the next.

29. An imaging device as in claim 23 wherein pixels of a parallel addressable group are sampled at least partially in parallel and digitized using sequential tasks which partially overlap selective reset tasks.

30. An imaging device as in claim 23 wherein pixels of a first parallel addressable group of pixels are first reset to begin a longest integration period and subsequently are subjected to a series of conditional resets to conditionally reset pixels on a pixel by pixel basis and to initiate a shorter integration period.

31. An imaging device as in claim 30 wherein determination to reset a pixel and to initiate a shorter integration period is based at least in part on a result of a comparison of an indication of a charge accumulated on any given pixel after partial integration to a threshold level.

32. An imaging device as in claim 30 wherein a record is maintained in a corresponding memory for each pixel indicating which integration period is currently active for any given pixel.

33. An imaging device as in claim 32 wherein said memory is fabricated on a common integrated circuit substrate with said array of pixels.

34. An imaging device as in claim 32 wherein said memory associated with pixels of an addressable group may be accessed substantially in parallel.

35. An imaging device as in claim 30 wherein conditional reset to begin a shorter integration period is bypassed for a pixel if a value recorded in said memory for said pixel indicates that said pixel was not reset during an immediately prior reset task for said pixel.

36. An imaging device in claim 30 wherein integrated charge on a pixel is digitized only once for each pixel which is read.

37. An imaging device as in claim 32 wherein dynamic memory is used for said memory associated with each pixel.

38. An imaging device as in claim 37 wherein said dynamic memory incorporates capacitive elements to store a bit value.

39. An imaging device as in claim 37 wherein refresh tasks for said dynamic memory are scheduled along with other tasks.

40. An imaging device, comprising:

an array of pixels partitioned into parallel addressable groups of pixels;

a pixel read task to read active pixels of an addressed parallel addressable group of pixels; and

multiple integration period initiating tasks each operable to initiate a different one of a set of available integration periods for selected pixels in an individually addressed parallel addressable group of pixels, said read task and each of said integration period initiating tasks are initiated at predetermined times in a task sequencing interval and each task is bypassed or assigned an addressable group of pixels with pixels on which to perform a given task.

41. An imaging device as in claim 40 configured to provide repetitious performance of tasks said task sequencing interval and assigns different parallel addressable groups of pixels to corresponding tasks for each of the task sequencing intervals such that substantially all tasks are performed on every parallel addressable group of pixels to complete image acquisition sequence.

42. An imaging device as in claim 40 wherein a task to establish the longest selectable integration period performs an unconditional reset of each pixel of an addressed parallel addressable group of pixels and each task to initiate one of a remaining, shorter, selectable integration periods first makes a determination, on a pixel by pixel basis, of pixels for which a shorter integration period is to be initiated and initiates said shorter integration period selectively by selective reset of said pixel.

43. An imaging device as in claim 40 wherein an indication of the integration period which is active for each pixel is recorded in a memory.

44. An imaging device as in claim 40 wherein an integration period initiated by a task in a particular task sequencing interval is established in part by the time that the task is initiated in the task sequencing interval and in part by the choice of the parallel addressable group of pixels selected to be operated on by the task.

45. An imaging device as in claim 40 wherein a parallel addressable group of pixels constitutes a substantial portion of a row of pixels in the imaging frame.

46. An imaging device as in claim 41 wherein total number times the tasks of the task sequencing interval are performed during a single image acquisition sequence equals or exceeds the number of parallel addressable groups having active pixels.

47. An imaging device as in claim 40 wherein tasks in a task sequencing interval are scheduled such that components shared by said tasks are used by only one task at a time.

48. An imaging device as in claim 40 wherein integration periods for at least some of the pixels read out in an image acquisition sequence begin before readout of all pixels of the preceding image acquisition sequence.

49. An imaging device as in claim 40 wherein dynamic memory is used for memory associated with each pixel.

50. An imaging device as in claim 49 wherein a task to refresh said dynamic memory is provided and scheduled during said task sequencing interval.

51. An imaging device comprising:

an array of pixels;

a set of available integration periods;

one of said set of available integration periods is selected and recorded in memory for substantially every pixel; and

at the end of an integration period, a reading of an integrated charge level on each pixel is digitized and output in a form that may be mapped directly into a mantissa of a floating point representation along with a corresponding indication of said integration period used to read said pixel is output in a form which may be mapped into an exponent of a floating point representation of a pixel value.

52. An imaging device as in claim 51 wherein a ratio in sensitivity for a pixel using a first available integration period relative to a second sensitivity using another of said available integration periods is approximately an integral power of 2.

53. An imaging device, comprising:

at least one parallel addressable group of pixels comprising a start of integration period for each pixel within said parallel addressable group of pixels dynamically determined within an image acquisition sequence; and

an end of integration for each pixel within said parallel addressable group of pixels that is substantially simultaneous for all pixels within said parallel addressable group of pixels.

54. An imaging device as in claim 53 wherein a start of integration for any given pixel within said parallel addressable group of pixels is independent of any other pixel within said parallel addressable group of pixels.

55. An imaging device as in claim 53 wherein at least one start of integration is selected from a set of available integration periods.

56. An imaging device as in claim 55 wherein said set of available integration periods is derived from an instruction prior to an image acquisition sequence.

57. An imaging device, comprising:

a two dimensional array of pixels and a memory register associated with each pixel of said two dimensional array of pixels for storing an indication of a selected integration period for a given pixel, wherein said selected integration period is selected from a set of at least four available integration periods based on at least one comparison during an image acquisition period.

58. An imaging device as in claim 57 wherein said memory register is at least partially outside an area defined by said two dimensional array of pixels.

59. An imaging device, comprising:

a two dimensional array of pixels; and

an image acquisition sequence comprising;

at least one conditional pixel reset task;

at least one integration period selection task; and

at least one pixel read task.

60. An imaging device as in claim 59 wherein said image acquisition sequence further comprises at least one unconditional pixel reset task.

61. An imaging device as in claim 59 wherein said at least one conditional pixel reset task, said at least one conditional pixel reset task and said at least one integration period selection task are scheduled according to a task sequencing interval within said image acquisition sequence.

62. An imaging device as in claim 60 wherein said at least one conditional pixel reset task, said at least one conditional pixel reset task, said at least one integration period selection task and said at least one unconditional pixel reset task are scheduled according to a task sequencing interval within said image acquisition sequence.