INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS

• US 20080192524A1
• Filed: 04/14/2008
• Published: 08/14/2008
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Luca G. Fasoli, Roy E. Scheuerlein
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G.
• Granted Patent: US 7,697,366 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

Claims

1. An integrated circuit comprising:

a memory array having a respective plurality of array lines of a first type for each of at least one memory layer;

a plurality of I/O bus lines;

a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines;

control circuitry for selectively enabling certain layer selector circuits, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether a second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented.

2. The integrated circuit as recited in claim 1 wherein:

if such second memory layer is not implemented, the given I/O bus line is coupled at such other times to an array line on the first memory layer.

3. The integrated circuit as recited in claim 1 wherein:

the array lines of the first type comprise bit lines;

the memory array further comprises a plurality of word lines, each word line comprising a word line segment on each of one or more word line layers; and

the integrated circuit further comprises a word line decoder having a configuration that is independent of whether the second memory layer is implemented.

4. The integrated circuit as recited in claim 2 wherein the plurality of layer selector circuits comprises:

layer selector circuits of a first type for coupling array lines on the first memory layer to a first group of said I/O bus lines;

layer selector circuits of a second type for coupling array lines on the second memory layer to the first group of said I/O bus lines;

layer selector circuits of a third type for coupling array lines on the first memory layer to a second group of said I/O bus lines; and

layer selector circuits of a fourth type for coupling array lines on the second memory layer to the second group of said I/O bus lines.

5. The integrated circuit as recited in claim 4 wherein:

each respective layer selector circuit of the first type and each respective layer selector circuit of the third type share a respective one of a first group of enable signals;

each respective layer selector circuit of the second type and each respective layer selector circuit of the fourth type share a respective one of a second group of enable signals that are disabled if the second memory layer is not implemented.

6. The integrated circuit as recited in claim 4 wherein:

each respective layer selector circuit of the first type and each respective layer selector circuit of the fourth type share a respective one of a first group of enable signals; and

each respective layer selector circuit of the second type and each respective layer selector circuit of the third type share a respective one of a second group of enable signals.

7. The integrated circuit as recited in claim 4 wherein:

the memory array is arranged in memory blocks;

each memory block that includes a layer selector circuit of the first type also includes a corresponding layer selector circuit of the fourth type, both responsive to the same enable signal; and

each memory block which includes a layer selector circuit of the second type also includes a corresponding layer selector circuit of the third type, both responsive to the same enable signal.

8. The integrated circuit as recited in claim 7 wherein:

memory blocks of a first type include layer selector circuits of the first type and the fourth type;

memory blocks of a second type include layer selector circuits of the second type and the third type; and

memory blocks of the first type alternate with memory blocks of the second type.

9. A integrated circuit comprising:

a memory array having at least one memory layer, each memory layer including a respective plurality of array lines of a first type;

means for configuring the memory array depending upon whether a second memory layer is implemented; and

means for coupling every respective one of a plurality of I/O bus lines for the memory array to a respective array line irrespective of whether the second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented.

10. The integrated circuit as recited in claim 9 wherein:

if such second memory layer is not implemented, the given I/O bus line is coupled at such other times to an array line on the first memory layer.

11. A method for use in an integrated circuit memory array having at least one memory layer, each memory layer including a respective plurality of array lines of a first type, said method comprising the steps of:

configuring the memory array depending upon whether a second memory layer is implemented;

simultaneously coupling every respective one of a plurality of I/O bus lines for the memory array to a respective array line irrespective of whether the second memory layer is implemented; and

coupling a given I/O bus line at times to an array line on the first memory layer, and at other times to an array line on the second memory layer if such second memory layer is implemented.

12. The method as recited in claim 11 wherein:

the given I/O bus line, if such second memory layer is not implemented, is coupled at such other times to an array line on the first memory layer.

13. The method as recited in claim 11 wherein:

when a first column select signal is enabled, respectively coupling array lines from the first memory layer to respective I/O bus lines of a first group, and respectively coupling array lines from a second memory layer, if implemented, to respective I/O bus lines of a second group; and

when a second column select signal is enabled, respectively coupling array lines from the second memory layer, if implemented, to respective I/O bus lines of the first group, and respectively coupling array lines from the first memory layer to respective I/O bus lines of the second group.

14. The method as recited in claim 13 further comprising:

individually enabling the first and second column select signals in a memory array in which both memory layers are implemented; and

simultaneously enabling the first and second column select signals in a memory array in which only the first memory layer is implemented.

15. The method as recited in claim 11 wherein:

when a first select signal is enabled, respectively coupling array lines from the first memory layer to respective I/O bus lines of a first group and of a second group; and

when a second select signal is enabled, respectively coupling array lines from the second memory layer, if implemented, to respective I/O bus lines of the first group and of the second group.

16. A method for making an integrated circuit product, said method comprising:

providing a memory array having a respective plurality of array lines of a first type for each of at least one memory layer;

providing a plurality of I/O bus lines;

providing a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines;

providing control circuitry for selectively enabling certain layer selector circuits, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether the second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented.

17. The method as recited in claim 16 wherein:

if such second memory layer is not implemented, the given I/O bus line is coupled at such other times to an array line on the first memory layer.

18. The method as recited in claim 16 wherein:

the array lines of the first type comprise bit lines;

the memory array further comprises a plurality of word lines, each word line comprising a word line segment on each of one or more word line layers; and

the integrated circuit further comprises a word line decoder having a configuration that is independent of whether the second memory layer is implemented.

19. The method as recited in claim 17 wherein the plurality of layer selector circuits comprises:

layer selector circuits of a first type for coupling array lines on the first memory layer to a first group of said I/O bus lines;

layer selector circuits of a second type for coupling array lines on the second memory layer to the first group of said I/O bus lines;

layer selector circuits of a third type for coupling array lines on the first memory layer to a second group of said I/O bus lines; and

layer selector circuits of a fourth type for coupling array lines on the second memory layer to the second group of said I/O bus lines.

20. The method as recited in claim 19 wherein:

each respective layer selector circuit of the first type and each respective layer selector circuit of the third type share a respective one of a first group of enable signals;

each respective layer selector circuit of the second type and each respective layer selector circuit of the fourth type share a respective one of a second group of enable signals that are disabled if the second memory layer is not implemented.

21. The method as recited in claim 19 wherein:

each respective layer selector circuit of the first type and each respective layer selector circuit of the fourth type share a respective one of a first group of enable signals; and

each respective layer selector circuit of the second type and each respective layer selector circuit of the third type share a respective one of a second group of enable signals.

22. The method as recited in claim 19 wherein:

the memory array is arranged in memory blocks;

each memory block that includes a layer selector circuit of the first type also includes a corresponding layer selector circuit of the fourth type, both responsive to the same enable signal; and

each memory block which includes a layer selector circuit of the second type also includes a corresponding layer selector circuit of the third type, both responsive to the same enable signal.

23. The method as recited in claim 22 wherein:

memory blocks of a first type include layer selector circuits of the first type and the fourth type;

memory blocks of a second type include layer selector circuits of the second type and the third type; and

memory blocks of the first type alternate with memory blocks of the second type.