HYBRID CIRCUIT HAVING NANOTUBE MEMORY CELLS

• US 20080192532A1
• Filed: 02/13/2008
• Published: 08/14/2008
• Est. Priority Date: 07/25/2001
• Status: Active Grant

• Current Assignee: Brent M. Segal, Darren K. Brock, Thomas Rueckes
• Original Assignee: Brent M. Segal, Darren K. Brock, Thomas Rueckes
• Inventors: Brock, Darren K., Rueckes, Thomas, SEGAL, BRENT M.
• Granted Patent: US 7,817,458 B2
• Time in Patent Office: Days
• US Class Current: 365/151
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: G11C 23/00 Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
• CPC Class Codes: Y10S 977/724 Devices having flexible or movable element
• CPC Class Codes: Y10S 977/734 Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/942 including protein logic element
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Claims

1. A method of forming a hybrid memory system comprising:

providing a substrate;

providing a nanotube fabric;

patterning the nanotube fabric;

providing electrical contacts to the nanotube fabric to form nanotube memory cells; and

forming semiconductor elements over the nanotube memory cells.

2. The method of claim 1, wherein forming nanotube memory cells comprises for each nanotube memory cell, forming a nanotube switch capable of switching states, wherein different switch states comprise different electrical pathways between the electrical contacts and the nanotube fabric.

3. The method of claim 1, further comprising performing a metallization step after forming the semiconductor elements.

4. The method of claim 1, further comprising performing a metallization step after providing electrical contacts to the nanotube fabric to form nanotube memory cells.

5. The method of claim 1, wherein providing a layer of nanotube fabric comprises growing the layer of nanotube fabric with carbon vapor deposition techniques.

6. The method of claim 1, wherein providing a layer of nanotube fabric comprises applying the layer of nanotube fabric with spin-coating techniques.

7. The method of claim 1, wherein forming the semiconductor elements over the nanotube memory cells comprises providing a cell selector circuit for selecting at least one corresponding nanotube memory cell.

8. The method of claim 1, wherein forming the semiconductor elements comprises fabricating CMOS devices.

9. The method of claim 1, wherein providing the electrical contacts to the nanotube fabric comprises providing one of a metal line and a semiconductor line.

10. The method of claim 9, wherein providing electrical contacts to the nanotube fabric further comprises providing a portion of n-doped silicon on top of the one of the metal line and the semiconductor line.

11. The method of claim 1, further comprising providing at least one intermediate structure disposed over the substrate, the intermediate structure providing a substantially planar surface upon which the nanotube fabric is disposed.

12. An intermediate structure for forming a hybrid memory circuit comprising:

a substrate;

a patterned region of nanotube fabric disposed over the substrate;

at least two electrical contacts disposed in electrical communication with the patterned region of nanotube fabric, the at least two electrical contacts in spaced relation from one another.

13. A method of forming a hybrid memory system comprising:

providing a substrate;

providing a nanotube fabric;

providing electrical contacts to the nanotube fabric;

forming a semiconductor layer over the nanotube fabric; and

patterning the nanotube fabric to provide nanotube memory cells and patterning the semiconductor layer to provide semiconductor elements in electrical communication with the nanotube memory elements.

14. The method of claim 13, wherein patterning the nanotube fabric to provide nanotube memory cells comprises providing for each nanotube memory cell a patterned region of nanotube fabric capable of switching states, different switch states corresponding to different memory states.

15. The method of claim 14, wherein the different switch states are non-volatile.

16. The method of claim 13, wherein patterning the semiconductor layer to provide semiconductor elements comprises forming a cell selector circuit for selecting at least one corresponding nanotube memory cell.

17. A hybrid memory system comprising:

a substrate;

patterned regions of nanotube fabric;

electrical contacts in electrical communication with the patterned regions of nanotube fabric, the electrical contacts and the pattered regions of nanotube fabric forming multiple nanotube memory cells capable of storing different memory states; and

semiconductor elements disposed over the nanotube memory cells.

18. The hybrid memory system of claim 17, wherein for each of the multiple nanotube memory cells, the corresponding patterned region of nanotube fabric comprises a nanotube switch capable of switching states, wherein different switch states correspond to the different memory states.

19. The hybrid memory system of claim 17, wherein the semiconductor elements disposed over the memory cells comprise cell selector circuitry for receiving memory address information and for selecting at least one corresponding memory cell in response thereto.