Semiconductor memory device and operating method thereof

• US 20080192558A1
• Filed: 02/11/2008
• Published: 08/14/2008
• Est. Priority Date: 02/13/2007
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Oishi, Kanji, Yoshida, Hiroyasu
• Granted Patent: US 7,859,933 B2
• Time in Patent Office: Days
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity

Abstract

A semiconductor memory device comprises an anti-fuse, a memory circuit including memory cells, and a peripheral circuit configured to access only an area of the memory circuit selected depending on a state of the anti-fuse.

Claims

1. A semiconductor memory device, comprising:

an anti-fuse;

a memory circuit including memory cells; and

a peripheral circuit configured to access only an area of said memory circuit selected depending on a state of said anti-fuse.

2. The semiconductor memory device according to claim 1,

wherein said peripheral circuit includes an input buffer for generating an internal address signal based on an external address signal supplied from outside and selects a memory cell to be accessed in said memory circuit in response to the internal address signal,

and the input buffer fixes a value of the internal address signal depending on the state of said anti-fuse.

3. The semiconductor memory device according to claim 1,

wherein said memory circuit includes a plurality of banks,

said peripheral circuit includes an input buffer for generating an internal bank address signal based on an external bank address signal supplied from outside and selects a bank to be accessed among the plurality of banks in response to the internal bank address signal,

and the input buffer fixes a value of the internal bank address signal depending on the state of said anti-fuse.

4. The semiconductor memory device according to claim 1, further comprising a plurality of data input/output terminals,

wherein said peripheral circuit includes:

a write/read circuit for sending write data from the plurality of data input/output terminals to said memory circuit and sending read data from said memory circuit to the plurality of data input/output terminals respectively in response to a first control signal and a second control signal; and

a switching circuit,

a portion of the write/read circuit corresponding to a first data input/output terminal of the plurality of the input/output terminals operates in response to the first control signal and a portion of the write/read circuit corresponding to a second data input/output terminal of the plurality of the input/output terminals operates in response to the second control signal,

and the switching circuit fixes a value of the first control signal or the second control signal depending on the state of said anti-fuse.

5. An operating method of a semiconductor memory device having an anti-fuse, a memory circuit including a memory cell array, and a peripheral circuit, comprising the steps of;

(a) setting a state of said anti-fuse according to a test result; and

(b) setting said peripheral circuit to access only an area of said memory circuit selected depending on the state of said anti-fuse.

6. The operating method of the semiconductor memory device according to claim 5, wherein said step (b) includes a step of fixing a row address of the memory cell array depending on the state of said anti-fuse.

7. The operating method of the semiconductor memory device according to claim 5,

wherein said memory circuit includes a plurality of banks,

and said step (b) includes a step of fixing a bank address of the memory cell array depending on the state of said anti-fuse.

8. The operating method of the semiconductor memory device according to claim 5,

wherein said peripheral circuit includes a write/read circuit for sending write data from a plurality of data input/output terminals to said memory circuit and sending read data from said memory circuit to the plurality of data input/output terminals respectively in response to a first control signal and a second control signal,

a portion of the write/read circuit corresponding to a first data input/output terminal of the plurality of the input/output terminals operates in response to the first control signal and a portion of the write/read circuit corresponding to a second data input/output terminal of the plurality of the input/output terminals operates in response to the second control signal,

and said step (b) includes a step of fixing a signal level of the first or second control signal depending on the state of said anti-fuse.