METHOD OF MANUFACTURING A 3-D CHANNEL FIELD-EFFECT TRANSISTOR AND AN INTEGRATED CIRCUIT
First Claim
Patent Images
1. A method of manufacturing an integrated circuit, the method comprising:
- forming an auxiliary structure between a first section and a second section of a field-effect transistor, wherein a first source/drain region is formed in the first section and a second source/drain region is formed in the second section;
removing a portion of the auxiliary structure to form a gap between the first section and a remaining portion of the auxiliary structure; and
forming a first insulator structure in the gap, wherein the first insulator structure separates the first source/drain region formed in the first section and the remaining portion of the auxiliary structure.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of manufacturing an integrated circuit includes providing an auxiliary structure between a first section and a second section of a field-effect transistor. A portion of the auxiliary structure is removed, where a gap is formed between the first section and a remaining portion of the auxiliary structure. In the gap, a first insulator structure is provided that separates a first source/drain region formed in the first section and a gate electrode formed between the first and the second section, where the second section may include a second source/drain region.
-
Citations
43 Claims
-
1. A method of manufacturing an integrated circuit, the method comprising:
-
forming an auxiliary structure between a first section and a second section of a field-effect transistor, wherein a first source/drain region is formed in the first section and a second source/drain region is formed in the second section; removing a portion of the auxiliary structure to form a gap between the first section and a remaining portion of the auxiliary structure; and forming a first insulator structure in the gap, wherein the first insulator structure separates the first source/drain region formed in the first section and the remaining portion of the auxiliary structure. - View Dependent Claims (2, 3, 4, 5, 32, 33)
-
-
6. A method of manufacturing a 3D-channel field-effect transistor, the method comprising:
-
forming a groove in a semiconductor substrate; disposing a fill material in a lower section of the groove; forming a top mask covering a first portion of the fill material and leaving a second portion of the fill material exposed; recessing the second portion to form a gap between the semiconductor substrate and the first portion; and forming a first insulator structure in the gap that separates a source/drain region disposed in the semiconductor substrate and a gate electrode disposed in the groove. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A method of manufacturing an integrated circuit including 3D-channel field-effect transistors, the method comprising:
-
forming a plurality of grooves in a semiconductor substrate; disposing a fill material in lower sections of the grooves; forming a plurality of top masks, each top mask covering a first portion of the fill material within each of the grooves and leaving a second portion of the fill material within each of the grooves exposed; recessing the second portions, wherein a gap is formed between each first portion and the semiconductor substrate; and forming in each gap a first insulator structure, wherein each first insulator structure separates a source/drain region that is formed in the semiconductor substrate and corresponds with respective groove and a gate electrode formed in the respective groove. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
34. A method of manufacturing an integrated circuit, the method comprising:
-
forming a gate electrode between a first section and a second section of a field-effect transistor, wherein a first source/drain region is formed in the first section and a second source/drain region is formed in the second section; removing a portion of the gate electrode to form a gap between the first section and a remaining portion of the gate electrode; and forming a first insulator structure in the gap, wherein the first insulator structure separates the first source/drain region formed in the first section and the remaining portion of the gate electrode. - View Dependent Claims (35, 36, 37, 38)
-
-
39. A method of manufacturing an integrated circuit comprising a field-effect transistor, the method comprising:
-
forming a source region, a drain region, and a channel region; forming a gate electrode having a lower edge below a lower edge of at least one of the source and drain regions; forming a gate dielectric between the channel region and the gate electrode; forming a first insulator structure between the gate electrode and at least a section of the source region; and forming a second insulator structure between the gate electrode and at least a section of the drain region, wherein at least one of the first and second insulator structures is structurally different from the gate dielectric and the first and the second insulator structures are asymmetric with respect to each other. - View Dependent Claims (40, 41, 42, 43)
-
Specification