METHOD OF MANUFACTURING A 3-D CHANNEL FIELD-EFFECT TRANSISTOR AND AN INTEGRATED CIRCUIT

• US 20080194068A1
• Filed: 02/13/2007
• Published: 08/14/2008
• Est. Priority Date: 02/13/2007
• Status: Abandoned Application

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Temmler, Dietmar, Sieck, Alexander, Gerber, Ralf
• Application Number:
  US11/674,167
• Publication Number:
  US 20080194068A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A method of manufacturing an integrated circuit includes providing an auxiliary structure between a first section and a second section of a field-effect transistor. A portion of the auxiliary structure is removed, where a gap is formed between the first section and a remaining portion of the auxiliary structure. In the gap, a first insulator structure is provided that separates a first source/drain region formed in the first section and a gate electrode formed between the first and the second section, where the second section may include a second source/drain region.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming an auxiliary structure between a first section and a second section of a field-effect transistor, wherein a first source/drain region is formed in the first section and a second source/drain region is formed in the second section;

removing a portion of the auxiliary structure to form a gap between the first section and a remaining portion of the auxiliary structure; and

forming a first insulator structure in the gap, wherein the first insulator structure separates the first source/drain region formed in the first section and the remaining portion of the auxiliary structure.

2. The method of claim 1, wherein forming the first insulator structure in the gap further comprises covering the gap without filling the gap, and the first insulator structure comprises a void.

3. The method of claim 1, wherein forming the first insulator structure in the gap further comprises filling the gap with an insulator material to form the first insulator structure.

4. The method of claim 1, wherein forming the first insulator structure in the gap further comprises growing a thermal oxide on a sidewall section of the first section to fill at least a section of the gap with the thermal oxide so as to form the first insulator structure.

5. The method of claim 1, wherein removing a portion of the auxiliary structure further comprises:

forming a top mask liner on the auxiliary structure, wherein an upper edge of the top mask liner is formed below an upper edge of the first and second sections;

performing an angled implantation to form an implanted section and an un-implanted section in the top mask liner;

removing one of the implanted section and the un-implanted section to form a top mask; and

recessing the auxiliary structure using the top mask as an etch mask.

32. The method of claim 1, wherein the remaining portion of the auxiliary structure forms a gate electrode of the field-effect transistor.

33. The method of claim 1, further comprising replacing the remaining portion of the auxiliary structure with a gate electrode material.

6. A method of manufacturing a 3D-channel field-effect transistor, the method comprising:

forming a groove in a semiconductor substrate;

disposing a fill material in a lower section of the groove;

forming a top mask covering a first portion of the fill material and leaving a second portion of the fill material exposed;

recessing the second portion to form a gap between the semiconductor substrate and the first portion; and

forming a first insulator structure in the gap that separates a source/drain region disposed in the semiconductor substrate and a gate electrode disposed in the groove.

7. The method of claim 6, wherein forming the first insulator structure further comprises:

covering the gap without filling the gap such that the first insulator structure comprises a void.

8. The method of claim 6, wherein forming the first insulator structure further comprises:

filling the gap with an insulator material to form the first insulator structure.

9. The method of claim 6, wherein forming the first insulator structure further comprises:

growing a thermal oxide on a sidewall section of the semiconductor substrate to fill at least a section of the gap with the thermal oxide to form the first insulator structure.

10. The method of claim 6, wherein forming a top mask further comprises:

forming a top mask liner on the fill material, wherein an upper edge of the top mask liner is formed below an upper edge of the groove;

performing an angled implantation to form an implanted section and an un-implanted section in the top mask liner; and

removing one of the implanted and the un-implanted section.

11. The method of claim 10, wherein the top mask liner comprises a silicon nitride liner.

12. The method of claim 6, wherein forming a top mask further comprises:

forming a top mask liner on the fill material, wherein an upper edge of the top mask liner is formed below an upper edge of the groove; and

performing an angled implantation to form an implanted section and an un-implanted section in the top mask liner, wherein the top mask liner is destroyed via the implant in the implanted section to form an exposed section.

13. The method of claim 12, wherein forming a top mask further comprises:

growing silicon oxide on the exposed section of the fill material to form the top mask covering the first portion of the fill material; and

removing the un-implanted section of the top mask liner to form the exposed section portion of the fill material.

14. The method of claim 6, further comprising, after recessing the second portion and before forming the first insulator structure:

introducing impurities into a substrate section exposed by recessing the second portion to form at least a portion of the source/drain region.

15. The method of claim 14, wherein the step of introducing impurities is performed by gas-phase diffusion.

16. The method of claim 6, further comprising, before forming the groove:

forming an oxide layer above the semiconductor substrate;

before disposing the fill material, forming a gate dielectric on an inner surface of the groove; and

performing a thermal oxidation to form a Bird'"'"'s Beak structure extending between the gate dielectric and the oxide layer.

17. The method of claim 6, further comprising, before forming the groove:

forming a spacer layer comprising an opening on a pattern surface of the semiconductor substrate, the opening forming a portion of the groove; and

forming a further portion of the groove in a section exposed by the opening;

wherein an upper edge of the fill material is provided above the pattern surface.

18. The method of claim 6, further comprising:

removing the top mask; and

forming symmetric insulator structures on opposing sections of an inner surface of the groove between an upper edge of the fill material and an upper edge of the semiconductor substrate.

19. The method of claim 18, wherein forming the symmetric insulator structures further comprises:

depositing a conformal insulator layer lining an upper section of the groove between the upper edge of the semiconductor substrate and the upper edge of the fill material; and

removing sections of the conformal insulator layer that are horizontally aligned in the substrate to form the symmetric insulator portions.

20. The method of claim 6, wherein the fill material forms the gate electrode.

21. The method of claim 6, further comprising, after forming a first insulator structure:

replacing the fill material with a gate electrode material forming the gate electrode.

22. A method of manufacturing an integrated circuit including 3D-channel field-effect transistors, the method comprising:

forming a plurality of grooves in a semiconductor substrate;

disposing a fill material in lower sections of the grooves;

forming a plurality of top masks, each top mask covering a first portion of the fill material within each of the grooves and leaving a second portion of the fill material within each of the grooves exposed;

recessing the second portions, wherein a gap is formed between each first portion and the semiconductor substrate; and

forming in each gap a first insulator structure, wherein each first insulator structure separates a source/drain region that is formed in the semiconductor substrate and corresponds with respective groove and a gate electrode formed in the respective groove.

23. The method of claim 22, wherein forming the first insulator structure further comprises:

covering the gaps without filling the gaps, such that the first insulator structures comprise voids.

24. The method of claim 22, wherein forming the first insulator structure further comprises:

filling each gap with an insulator material to form the first insulator structures.

25. The method of claim 22, wherein forming the first insulator structure further comprises:

growing a thermal oxide on an exposed section of the inner surface of the groove to fill at least a section of each gap with an insulator material to form the first insulator structures.

26. The method of claim 22, further comprising, before forming the plurality of grooves:

forming a spacer layer comprising openings on a pattern surface of the semiconductor substrate, each opening forming a portion of a respective groove; and

forming further portions of the grooves in sections exposed by the openings;

wherein an upper edge of the fill material is provided above the pattern surface.

27. The method of claim 26, further comprising:

removing the spacer layer to expose protrusion portions of the fill material protruding from the semiconductor substrate, wherein each protrusion portion is aligned with a respective groove.

28. The method of claim 27, further comprising:

forming etch stop spacers on the vertical sidewalls of the protrusion portions.

29. The method of claim 27, further comprising:

filling spaces between the protrusion portions with base layers, wherein an upper edge of each base layer is flush with the upper edge of the protrusion portions that are adjacent the base layer;

depositing a conductive layer on a process surface formed by upper edges of each base layer and the protrusion portions adjacent the base layer; and

patterning the conductive layer and the base layers to form parallel word lines.

30. The method of claim 22, further comprising,

removing the top mask;

and

forming pairs of symmetric insulator structures on opposing sections of an inner surface of each groove between an upper edge of the semiconductor substrate and an upper edge of the fill material.

31. The method of claim 30, wherein forming the symmetric insulator sections further comprises:

depositing a conformal insulator layer lining upper sections of the grooves between the upper edge of the semiconductor substrate and the upper edge of the fill material; and

removing sections of the conformal insulator layer that are aligned horizontally within the semiconductor substrate to form the symmetric insulator portions.

34. A method of manufacturing an integrated circuit, the method comprising:

forming a gate electrode between a first section and a second section of a field-effect transistor, wherein a first source/drain region is formed in the first section and a second source/drain region is formed in the second section;

removing a portion of the gate electrode to form a gap between the first section and a remaining portion of the gate electrode; and

forming a first insulator structure in the gap, wherein the first insulator structure separates the first source/drain region formed in the first section and the remaining portion of the gate electrode.

35. The method of claim 34, wherein forming the first insulator structure in the gap further comprises covering the gap without filling the gap, and the first insulator structure comprises a void.

36. The method of claim 34, wherein forming the first insulator structure in the gap further comprises filling the gap with an insulator material to form the first insulator structure.

37. The method of claim 34, wherein forming the first insulator structure in the gap further comprises growing a thermal oxide on a sidewall section of the first section to fill at least a section of the gap with the thermal oxide so as to form the first insulator structure.

38. The method of claim 34, wherein removing a portion of the gate electrode further comprises:

forming a top mask liner on the gate electrode, wherein an upper edge of the top mask liner is formed below an upper edge of the first and second sections;

performing an angled implantation to form an implanted section and an un-implanted section in the top mask liner;

removing one of the implanted section and the un-implanted section to form a top mask; and

recessing the gate electrode using the top mask as an etch mask.

39. A method of manufacturing an integrated circuit comprising a field-effect transistor, the method comprising:

forming a source region, a drain region, and a channel region;

forming a gate electrode having a lower edge below a lower edge of at least one of the source and drain regions;

forming a gate dielectric between the channel region and the gate electrode;

forming a first insulator structure between the gate electrode and at least a section of the source region; and

forming a second insulator structure between the gate electrode and at least a section of the drain region, wherein at least one of the first and second insulator structures is structurally different from the gate dielectric and the first and the second insulator structures are asymmetric with respect to each other.

40. The method of claim 39, wherein the gate electrode is formed between the source region and the drain region.

41. The method of claim 39, wherein at least one of the first and second insulator structures is formed to have a different thicknesses than the gate dielectric.

42. The method of claim 39, wherein at least one of the first and second insulator structures is formed to extend into a semiconductor substrate to a different depth than the gate dielectric.

43. The method of claim 39, wherein at least one of the first and second insulators is formed of a different material than the gate dielectric.