Integrated Circuit Transformer Devices for On-Chip Millimeter-Wave Applications

• US 20080195988A1
• Filed: 04/21/2008
• Published: 08/14/2008
• Est. Priority Date: 04/08/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Benny Sheinman, David J. Goren, Shlomo Shlafman, Ullrich R. Pfeiffer
• Inventors: Shlafman, Shlomo, Goren, David, Sheinman, Benny, Pfeiffer, Ullrich R.
• Granted Patent: US 8,122,393 B2
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03F 3/26 Push-pull amplifiers; Phase-splitters therefor duplicated single-ended push-pull arrangements or phase-splitters therefor H03F3/30
• CPC Class Codes: H03F 3/45089 Non-folded cascode stages
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers

Abstract

Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.

Claims

1. A method of fabricating a semiconductor device, comprising forming a ground shield, a primary conductor and a secondary conductor, wherein forming the ground shield comprises patterning a layer of conductive material to form close-ended parallel elongated slots that are disposed orthogonal to the primary and secondary conductors, and edge regions that provide current return paths collinear to the primary and secondary conductors.

2. The method of claim 1, wherein the ground shield, primary conductor and secondary conductor are formed on different layers of an integrated circuit to form a stacked transformer device.

3. The method of claim 2, wherein the ground shield, the primary conductor and secondary conductor are formed from different metallization layers using a BEOL process.

4. A computer implemented method for integrated ciruit design and simulation, comprising:

generating a virtual model of a circuit using a model for each component of the circuit, wherein at least one model comprises a lumped equivalent circuit representation of an integrated circuit transformer structure having stacked primary and secondary conductors over a ground plane with, in which conductor length is a user-specified parameter;

performing a simulation of the circuit based on one or more user-specified parameter values for conductor length; and

presenting results of the simulation.

5. The method of claim 4, wherein the lumped equivalent circuit representation of the integrated transformer comprises an RLC filter network.

6. The method of claim 5, wherein generating a virtual model comprises:

providing a user interface that allows a user to build a schematic depiction of the circuit using schemtic icon depictions of the circuit components; and

obtaining a model corresponding to each schematic icon depiction from a library of predefined models.

7. The method of claim 5, wherein generating a virtual model comprises:

providing a user interface that allows a user to build a 3D circuit layout representation of the circuit;

performing a 3D EM analysis of the 3D circuit; and

generating a equivalent model for each circuit component using results of the 3D EM analysis.