Diode Having Reduced On-resistance and Associated Method of Manufacture

• US 20080197360A1
• Filed: 02/16/2007
• Published: 08/21/2008
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Hagleitner, Helmut, Sriram, Saptharishi, Smith, Thomas J.
• Granted Patent: US 8,138,583 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide.

Claims

1. A laterally conductive diode comprising:

a first doped semiconductor layer having a first surface;

a semiconductor mesa on said first surface of said first doped layer;

a top ohmic contact on said mesa;

a nonconductive mesa sidewall spacer covering at least a portion of the side of said mesa between said first surface of said first doped layer and the top of said mesa;

a lateral ohmic contact extending across at least a portion of said first surface of said first doped layer, said lateral ohmic contact conducting a current from said top ohmic contact laterally across said first doped layer.

2. A laterally conductive diode according to claim 1, wherein said lateral ohmic contact extends from said sidewall spacer.

3. A laterally conductive diode according to claim 1, wherein said top ohmic contact extends across said mesa to a position adjacent said sidewall spacer.

4. A laterally conductive diode according to claim 1, wherein said mesa comprises an intrinsic semiconductor region and a region having a different conductivity type from said first doped layer.

5. A laterally conductive diode according to claim 4, wherein said first doped layer is of n+ doping type.

6. A laterally conductive diode according to claim 5, wherein said region of different conductivity type is of p+ doping type.

7. A laterally conductive diode according to claim 1, wherein said mesa comprises an n−

doping type semiconductor.

8. A laterally conductive diode according to claim 1, further comprising a conductive metal cathode on said lateral ohmic contact.

9. A laterally conductive diode according to claim 1, further comprising a conductive metal anode on said top ohmic contact.

10. A laterally conductive diode according to claim 1, wherein said top ohmic contact comprises a metal silicide.

11. A laterally conductive diode according to claim 10, wherein said metal silicide is selected from the group consisting of TiSi₂, CoSi₂, and Ni₂Si.

12. A laterally conductive diode according to claim 1, further comprising a conductive metal cathode on said lateral ohmic contact.

13. A laterally conductive diode according to claim 12, wherein said metal silicide is selected from the group consisting of TiSi₂, CoSi₂, and Ni₂Si.

14. A laterally conductive diode according to claim 1, wherein said first doped layer is on a semi-insulating substrate.

15. A laterally conductive diode according to claim 14, wherein said semi-insulating substrate is a silicon carbide substrate.

16. A laterally conductive diode according to claim 14, further comprising a bottom contact on the side of said substrate opposite said n+ layer for mounting the diode in a circuit.

17. A PIN diode comprising:

an n+ type doped semiconductor layer having a first surface;

an intrinsic semiconductor layer on said first surface of said n+ semiconductor layer for controlling the current through the diode;

a p+ semiconductor layer on said intrinsic layer;

a top ohmic contact on said p+ type semiconductor layer;

a lateral ohmic contact on said first surface of said n+ type semiconductor layer, said lateral ohmic contact positioned proximate to said intrinsic layer and said p+ layer, wherein the PIN diode conducts a current from said top ohmic contact to said lateral ohmic contact across said n+ layer.

18. A PIN diode according to claim 17, further comprising a cathode on said lateral ohmic contact.

19. A PIN diode according to claim 17, wherein said lateral ohmic contact is a metal silicide.

20. A PIN diode according to claim 19, wherein said metal silicide is selected from the group consisting of TiSi₂, CoSi₂, and Ni₂Si.

21. A PIN diode according to claim 17, wherein said top ohmic contact is a metal silicide.

22. A PIN diode according to claim 21, wherein said metal silicide is selected from the group consisting of TiSi₂, CoSi₂, and Ni₂Si.

23. A PIN diode according to claim 17, further comprising a sidewall spacer covering at least one side of both said intrinsic layer and said p+ layer, wherein said sidewall spacer faces said lateral ohmic contact to prevent short circuiting between said top ohmic contact and said lateral ohmic contact.

24. A PIN diode according to claim 23, wherein said sidewall spacer is selected from the group consisting of silicon dioxide and silicon nitride.

25. A laterally conductive diode according to claim 23, wherein said lateral ohmic contact extends from said sidewall spacer.

26. A laterally conductive diode according to claim 23, wherein said top ohmic contact extends across said mesa to a position adjacent said sidewall spacer.

27. A PIN diode according to claim 17, wherein said n+ layer is on a silicon carbide substrate.

28. A PIN diode according to claim 24, further comprising a bottom contact on the side of said substrate opposite said n+ layer for mounting the PIN diode in a circuit.

29. A method of forming a diode, comprising:

forming a semiconductor mesa on a first surface of a first doped semiconductor layer,

depositing a nonconductive spacer material on at least one side of the mesa from the top of the mesa to the first doped layer to form at least one sidewall spacer for preventing short circuiting within the diode;

forming a lateral ohmic contact on the first surface of the first doped layer;

forming top ohmic contact on the mesa;

wherein the diode conducts a current from the top ohmic contact to the lateral ohmic contact in a conductive path that extends laterally across the first doped layer through a portion of the lateral ohmic contact on the first doped layer.

30. A method of forming a diode according to claim 29, wherein the step of forming the mesa comprises forming an n−

type semiconductor layer on an n+ type silicon carbide layer to form a Schottky diode.

31. A method of forming a diode according to claim 29, wherein the step of forming the mesa comprises forming an intrinsic silicon carbide layer on a first doped layer of n+ silicon carbide layer, and forming a p+ silicon carbide layer on the intrinsic silicon carbide layer to form a PIN diode.

32. A method of forming a diode according to claim 29, wherein the step of forming the lateral ohmic contact comprises reacting silicon and a conductive metal on the surface of the first doped semiconductor layer between the sidewall spacer and the lateral ohmic contact.

33. A method of forming a diode according to claim 29, wherein the step of forming the top and lateral ohmic contacts comprises:

depositing a layer of silicon over the first semiconductor layer, the mesa, and the sidewall spacer;

removing the silicon from the sidewall spacer;

depositing a conductive metal over the mesa, the sidewall spacer and at least a portion of the first semiconductor layer; and

heating the silicon and metal to a temperature sufficient to react the silicon with the conductive metal.

34. A method according to claim 33, wherein the silicon and metal are heated to a temperature between about 300 and 400 degrees Celsius to form a lateral ohmic contact and a top ohmic contact of metal silicide.

35. A method according to claim 34, wherein the conductive metal is removed from the sidewall spacer.

36. A method according to claim 29, wherein the diode is heated to a temperature of about 800 degrees Celsius to activate the dopants.

37. A method of forming a PIN diode, comprising:

forming a semiconductor mesa on a first surface of an n+ type semiconductor layer, wherein the semiconductor mesa includes an intrinsic semiconductor layer on the n+ type layer and a p+ type layer on the intrinsic layer;

forming a top ohmic contact on the mesa;

forming a lateral ohmic contact on the n+ layer adjacent but not touching the mesa;

wherein the conductive path of the diode extends laterally across the n+ layer and through a portion of the lateral ohmic contact.

38. A method of forming a PIN diode according to claim 37, further comprising the step of, prior to forming the ohmic contacts, forming at least one sidewall spacer on the mesa to prevent short circuiting within the diode, wherein the sidewall spacer is formed by depositing a nonconductive spacer material on at least one side of the mesa from the top of the mesa to the n+ type layer.

39. A method of forming a PIN diode according to claim 38, wherein the steps of forming the top ohmic contact and the lateral ohmic contact comprise forming metal silicide ohmic contacts.

40. A method of forming a diode according to claim 39, wherein the step of forming the metal silicide comprises reacting silicon and a conductive metal across at least a portion of the surface of the first n+ type layer adjacent the sidewall spacer.

41. A method of forming a diode according to claim 39, wherein the step of forming the metal silicide comprises:

depositing a layer of silicon over the first semiconductor layer, the mesa, and the sidewall spacer;

removing the silicon from the sidewall spacer;

depositing a conductive metal over the mesa, the sidewall spacer and at least a portion of the first semiconductor layer; and

heating the silicon and metal to a temperature sufficient to react the silicon with the conductive metal.

42. A method according to claim 41, wherein the silicon and metal are heated to a temperature between about 300 and 400 degrees Celsius to form ohmic contacts of metal silicide on the mesa and on the surface of the n+ layer.

43. A method according to claim 42, wherein the conductive metal is removed from the sidewall spacer.

44. A method according to claim 37, wherein the diode is heated to a temperature of about 800 degrees Celsius to anneal the ohmic contacts.

45. A method of directing current across a diode, comprising:

forming a silicon carbide mesa on a first doped silicon carbide layer;

passivating at least one side of the mesa to prevent short circuiting along the side of the mesa;

forming a lateral ohmic contact on the exposed region of the first doped silicon carbide layer, the lateral ohmic contact extending from the passivated side of the mesa to provide an electrical connection for current flowing from the mesa across the first silicon carbide layer.

46. A method according to claim 45, wherein the step of forming the semiconductor mesa comprises forming an intrinsic silicon carbide layer on the first silicon carbide layer and forming a p+ type silicon carbide layer on the intrinsic layer.

47. A method according to claim 45, wherein the step of passivating the mesa comprises depositing a passivation material selected from the group consisting of silicon dioxide and silicon nitride onto the first silicon carbide layer and onto the mesa.

48. A method according to claim 47, wherein the step of passivating the mesa comprises etching the passivation material from the top of the mesa and from a portion of the first silicon carbide layer, leaving the passivation material on the sides of the mesa.

49. A method according to claim 45, wherein the step of forming the lateral ohmic contact comprises forming an ohmic contact of a metal silicide.

50. A method according to claim 45, further comprising the step of forming a metal silicide top ohmic contact on the mesa.

51. A method of forming a diode according to claim 50, wherein the step of forming the metal silicide comprises:

depositing a layer of silicon over the first semiconductor layer, the mesa, and the sidewall spacer;

removing the silicon from the sidewall spacer;

depositing a conductive metal over the mesa, the sidewall spacer and at least a portion of the first semiconductor layer; and

heating the silicon and metal to a temperature sufficient to react the silicon with the conductive metal.

52. A method according to claim 51, wherein the silicon and metal are heated to a temperature between about 300 and 400 degrees Celsius to form ohmic contacts of metal silicide on the mesa and on the surface of the n+ layer.

53. A method according to claim 52, wherein the conductive metal is removed from the sidewall spacer.

54. A method according to claim 53, wherein the diode is heated to a temperature of about 800 degrees Celsius to anneal the ohmic contacts.