Sensing FET integrated with a high-voltage vertical transistor

• US 20080197406A1
• Filed: 02/16/2007
• Published: 08/21/2008
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Parthasarathy, Vijay, Manley, Martin H.
• Granted Patent: US 8,653,583 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A semiconductor device comprising:

a main vertical transistor, which comprises;

a substrate of a first conductivity type;

a pillar of semiconductor material disposed above the substrate, the pillar having a width and a length that extends in a first lateral direction, a first source region comprising one or more regions of the first conductivity type disposed at or near a top surface of the pillar, a body region of a second conductivity type being disposed in the pillar beneath the first source region, an extended drain region of the first conductivity type being disposed in the pillar beneath the body region;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions;

first and second gate members respectively disposed in the first and second dielectric regions at or near the top surface of the pillar adjacent the body region, the first and second gate members being separated from the body region by a gate oxide having a first thickness;

a sensing transistor, which comprises;

a second source region of the first conductivity type disposed at or near a top surface of the pillar, the second source region being separated in the first lateral direction from the first source region by an area of the body region that extends to the top surface of the pillar,

wherein the sensing transistor is operable to sample a small portion of a current that flows in the main vertical transistor.

2. The semiconductor device of claim 1 wherein the pillar is arranged in a racetrack-shaped layout.

3. The semiconductor device of claim 1 further comprising:

a source electrode that electrically contacts the one or more first source regions;

a sensing source electrode that electrically contacts the second source region; and

a drain electrode that electrically contacts a bottom surface of the substrate.

4. The semiconductor device of claim 1 further comprising an extended drain region disposed in the pillar beneath the body region.

5. The semiconductor device of claim 1 wherein the length in the first lateral direction is at least 30 times greater than the width.

6. The semiconductor device of claim 1 wherein the first and second gate members are insulated from the first and second field plates.

7. The semiconductor device of claim 1 wherein the first source region further comprises one or more regions of the second conductivity type disposed at or near a top surface of the pillar, the one or more regions of the first and second conductivity types being arranged in an alternating manner in the first lateral direction such that each of the one or more regions of the first conductivity type adjoins one of the one or more regions of the second conductivity type.

8. A semiconductor device comprising:

a main vertical field-effect transistor (FET); and

a sensing FET, the main vertical FET and the sense FET both being formed on a pillar of semiconductor material formed on a substrate of a first conductivity type, the pillar having a width and a length that extends in a first lateral direction, first and second dielectric regions being disposed on opposite sides of the pillar, first and second gate members being respectively disposed adjacent the pillar in the first and second dielectric regions at or near the top surface of the pillar body region, the main vertical FET and the sense FET both sharing an extended drain region of the first conductivity type formed in the pillar above the substrate, the first and second gate members also being commonly shared by the main vertical FET and the sense FET;

the main vertical FET further including;

a first body region of a second conductivity type disposed in the pillar above the extended drain region; and

a first source region disposed at or near the top surface of the pillar, the source region being vertically separated from the extended drain region by the first body region;

the sensing FET further including;

a second body region of a second conductivity type disposed in the pillar above the extended drain region; and

a second source region disposed at or near the top surface of the pillar, the second source region being vertically separated from the extended drain region by the second body region, the second source region being separated and electrically isolated in the first lateral direction from the first source region,

wherein the sensing FET is operable to sample a small portion of a current that flows in the main vertical FET.

9. The semiconductor device of claim 8 further comprising first and second field plates respectively disposed in the first and second dielectric regions.

10. The semiconductor device of claim 9 further comprising:

a source electrode that electrically contacts the first source region;

a sensing source electrode that electrically contacts the second source region; and

a drain electrode that electrically contacts a bottom surface of the substrate.

11. The semiconductor device of claim 10 wherein the source electrode also electrically contacts the first and second field plates.

12. The semiconductor device of claim 8 wherein an area of the extended drain region extends to the top surface of the pillar between the first and second body regions.

13. The semiconductor device of claim 12 wherein the first body region extends to the top surface of the pillar on opposite sides of the first source region in the first lateral direction, and the second body region extends to the top surface of the pillar on opposite sides of the second source region in the first lateral direction.

14. The semiconductor device of claim 8 wherein the first and second body regions comprise a single body region common to the main vertical FET and the sensing FET, an area of the single body region extending to the top surface of the pillar between the first and second source regions.

15. The semiconductor device of claim 8 wherein the pillar is arranged in a racetrack-shaped layout, the length of the pillar being at least 30 times greater than the width.

16. A semiconductor device comprising:

a plurality of transistor segments arranged in a side-by-side relationship, each transistor segment including;

a pillar of semiconductor material formed a racetrack-shaped layout on a substrate of a first conductivity type, the pillar having a length that extends in a first lateral direction and a width, the pillar having a source region disposed at or near a top surface of the pillar, an extended drain region, and a body region of a second conductivity type that vertically separates the source and extended drain regions;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second gate members respectively disposed in the first and second dielectric regions at or near a top of the pillar adjacent the body region;

first and second field plates respectively disposed in the first and second dielectric regions;

a source electrode that electrically contacts the source region of a majority of the transistor segments, the source electrode being associated with a main vertical transistor;

a sensing electrode that electrically contacts the source region of a minority of the transistor segments, the sensing electrode being associated with a sensing transistor that is operable to sample a small portion of a current that flows in the main vertical transistor; and

a drain electrode that electrically contacts a bottom surface of the substrate, the drain electrode and the first and second gate members each being common to the main vertical transistor and the sensing transistor.

17. The semiconductor device of claim 16 wherein the minority of the transistor segments comprises a single transistor segment.

18. The semiconductor device of claim 16 wherein the source electrode electrically contacts the first and second field plate of all of the transistor segments.

19. The semiconductor device of claim 16 wherein the source electrode electrically contacts the second field plate of all of the transistor segments and the first field plate of the majority of the transistor segments associated with the main vertical transistor, the sensing electrode electrically contacting the first field plate of the minority of the transistor segments associated with the sensing transistor.

20. The semiconductor device of claim 16 wherein the length in the first lateral direction is at least 30 times greater than the width.

21. The semiconductor device of claim 16 wherein the first and second gate members are insulated from the first and second field plates.

22. The semiconductor device of claim 16 wherein the source region comprises first regions of the first conductivity type and second regions of the second conductivity type, the first and second regions being arranged in an alternating manner in the first lateral direction such that each of the first regions adjoins one of the second regions.