CHIP PACKAGE

• US 20080197503A1
• Filed: 10/22/2007
• Published: 08/21/2008
• Est. Priority Date: 02/15/2007
• Status: Abandoned Application

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Hsu, Chi-Hsing
• Application Number:
  US11/876,381
• Publication Number:
  US 20080197503A1
• Time in Patent Office: Days
• US Class Current: 257/763
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/92227 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19051 : Impedance matching structure [e.g. balun]
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A chip package including a carrier, at least one chip disposed on the carrier, a plurality of wires electrically connecting the carrier and the chip, and an encapsulant wrapping the chip and the wires is provided. The chip has a semiconductor substrate, an interconnection structure, at least one first reference plane, at least one second reference plane, and at least one chip via, in which the first and second reference planes are respectively located on both sides of the semiconductor substrate, and the interconnection structure is located on the first reference plane and the semiconductor substrate. The chip via connects the first reference plane to the second reference plane. The chip package further includes at least one conductive bonding layer, which bonds the second reference plane to the carrier.

Claims

1. A chip package, comprising:

a carrier, having a first carrier surface;

at least one chip, having a semiconductor substrate, an interconnection structure, at least one first reference plane, at least one second reference plane, and at least one chip via, wherein the semiconductor substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface, the first reference plane and the second reference plane are respectively located on the first substrate surface and the second substrate surface, the interconnection structure is located on the first reference plane and the first substrate surface and has at least one chip signal pad, and the chip via connects the first reference plane to the second reference plane;

at least one conductive bonding layer, bonding the second reference plane to the first carrier surface of the carrier;

at least one wire, connecting the chip signal pad to the first carrier surface of the carrier; and

an encapsulant, wrapping the chip and the wire.

2. The chip package as claimed in claim 1, wherein the first reference plane is a ground plane or a power plane, and the second reference plane is the ground plane or the power plane corresponding to the first reference plane.

3. The chip package as claimed in claim 1, wherein the second reference plane comprises a gold layer.

4. The chip package as claimed in claim 1, wherein the second reference plane is a composite layer comprising a Ti layer, a Cu layer, and a Ni layer.

5. The chip package as claimed in claim 1, wherein the second reference plane is a composite layer comprising a Ti layer, a Ni—

V layer, and a Cu layer.

6. The chip package as claimed in claim 1, wherein the chip via passes through an internal part of the semiconductor substrate to connect the first reference plane to the second reference plane.

7. The chip package as claimed in claim 1, wherein the chip via bypasses an external side of the semiconductor substrate to connect the first reference plane to the second reference plane.

8. The chip package as claimed in claim 1, wherein the carrier has at least one carrier signal pad located on the first carrier surface of the carrier, and the wire connects the chip signal pad to the carrier signal pad.

9. The chip package as claimed in claim 1, wherein the carrier has at least one first reference pad located on the first carrier surface of the carrier, and the conductive bonding layer bonds the second reference plane to the first reference pad.

10. The chip package as claimed in claim 9, wherein the carrier has a second carrier surface opposite to the first carrier surface, at least one second reference pad, and at least one carrier via, the second reference pad is located on the second carrier surface, and the carrier via connects the first reference pad to the second reference pad.

11. The chip package as claimed in claim 10, further comprising at least one conductor connected to the second reference pad.

12. The chip package as claimed in claim 1, wherein the chip further comprises an electronic device disposed on the first substrate surface.

13. The chip package as claimed in claim 12, wherein the electronic device is electrically connected to the first reference plane through the interconnection structure.

14. The chip package as claimed in claim 12, wherein the electronic device is electrically connected to the carrier through the interconnection structure and the wire.

15. The chip package as claimed in claim 1, wherein the first reference plane is annular shaped.

16. The chip package as claimed in claim 1, wherein the second reference plane is annular shaped.