Apparatus and Method For Determining Reliability Of An Integrated Circuit

• US 20080197870A1
• Filed: 08/23/2007
• Published: 08/21/2008
• Est. Priority Date: 08/23/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Koerner, Heinrich
• Granted Patent: US 7,684,949 B2
• Time in Patent Office: Days
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2843 In-circuit-testing
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if the measurement quantity determined does not correspond to predefined criteria, a corresponding signal is output.

Claims

1. A method for determining the reliability of a chip, comprising:

providing the chip in its intended application environment;

determining a measurement quantity representing the state of one or a plurality of electrical connections in the chip within the application environment of the chip; and

outputting a signal if the determined measurement quantity does not correspond to a predefined criterion.

2. The method of claim 1, wherein the measurement quantity is determined with regard to a selected electrical connection structure.

3. The method of claim 1, wherein the measurement quantity is determined in a temporally continuous manner.

4. The method of claim 1, wherein the measurement quantity is determined in predetermined time intervals and/or under predetermined conditions.

5. The method of claim 1, wherein the measurement quantity is the electrical resistance.

6. The method of claim 1, wherein a change in the measurement quantity with respect to time is determined.

7. The method of claim 1, wherein a threshold value is predefined as a criterion for the measurement quantity and the signal is output if the threshold value is overshot or undershot.

8. A method for determining an item of information with regard to the state of an electrical connection in a chip having a plurality of metallization levels and at least one via connection between two metallization levels, the method comprising:

determining a measurement quantity with regard to a selected electrical connection structure containing at least one via connection; and

outputting a signal if the determined measurement quantity does not correspond to predefined criteria.

9. The method of claim 8, wherein the chip is supplied to its intended application and the measurement quantity is determined within the application environment of the chip.

10. The method of claim 8, wherein the measurement quantity is determined in a temporally continuous manner.

11. The method of claim 8, the measurement quantity is determined in predetermined time intervals and/or under predetermined conditions.

12. The method of claim 8, wherein the measurement quantity is electrical resistance.

13. The method of claim 8, further comprising determining a change in the measurement quantity over time.

14. The method of claim 8, wherein a threshold value is predefined as a criterion for the measurement quantity and the signal is output if the threshold value is overshot or undershot.

15. An apparatus for determining the reliability of a chip supplied to its intended application and within the application environment of the chip, comprising:

a measuring circuit determining a measurement quantity representing a state of an electrical connection in the chip, said circuit outputting a corresponding signal if the measurement quantity does not correspond to predefined criteria.

16. The apparatus of claim 15, wherein said measuring circuit selects an electrical connection structure contained in the chip and determines the measurement quantity with regard to the selected electrical connection structure.

17. The apparatus of claim 15, wherein said circuit determines the electrical resistance as the measurement quantity.

18. The apparatus of claim 15, wherein said circuit determines the measurement quantity in a temporally continuous manner.

19. The apparatus of claim 15, wherein said circuit determines the measurement quantity in predetermined time intervals and/or under predetermined conditions.

20. The apparatus of claim 15, wherein said circuit determines the change in the measurement quantity over time.

21. The apparatus of claim 15, wherein said circuit outputs the signal if a threshold value that is predefined for the measurement quantity or for a quantity derived from the measurement quantity is overshot or undershot.

22. An apparatus for determining an item of information with regard to the state of an electrical connection in a chip having a plurality of metallization levels and at least one via connection between two metallization levels, said apparatus comprising:

a measuring circuit determining a measurement quantity with regard to a selected electrical connection structure containing at least one via connection, the measuring circuit outputting a corresponding signal if the measurement quantity does not correspond to predefined criteria.

23. The apparatus of claim 22, wherein the measurement circuit determines the measurement quantity within the application environment of the chip and, if appropriate, outputs the signal.

24. The apparatus of claim 22, wherein the measurement circuit determines the measurement quantity in a temporally continuous manner.

25. The apparatus of claim 22, wherein the measurement circuit determines the measurement quantity in predetermined time intervals and/or under predetermined conditions.

26. The apparatus of claim 22, wherein the measurement circuit determines the electrical resistance as the measurement quantity.

27. The apparatus of claim 22, wherein the measurement circuit determines a change in the measurement quantity over time.

28. The apparatus of claim 22, wherein the measurement circuit outputs the signal if a threshold value that is predefined for the measurement quantity or for a quantity derived from the measurement quantity is overshot or undershot.

29. A semiconductor chip, comprising:

an electrical interconnect system; and

an electrical connection structure for testing the reliability of the chip, said structure being arranged outside the electrical interconnect system.

30. The chip of claim 29, wherein the electrical connection elements contained in the electrical connection structure are produced in the same way and/or together with structurally identical electrical connection elements of the electrical interconnect system.

31. The chip of claim 29, wherein the electrical interconnect system has a plurality of metallization levels, and the electrical connection structure has a via connection and/or a contact between a via connection and a connecting region and/or another electrical connection, the connecting region being arranged in a level that is coplanar with one of the metallization levels of the electrical interconnect system.

32. An apparatus, comprising:

a chip supplied to its intended application; and

a measuring circuit, said circuit determining a measurement quantity representing a state of an electrical connection in the chip, said measuring circuit outputting a corresponding signal if the measurement quantity does not correspond to a predefined criteria.

33. The apparatus of claim 32, wherein the measuring circuit selects an electrical connection structure in the chip, and determines the measurement quantity with regard to the selected electrical connection structure.

34. The apparatus of claim 32, wherein the chip has an electrical interconnect system and the electrical connection structure is a part of the interconnect system.

35. The apparatus of claim 32, wherein the chip has an electrical interconnect system, and the electrical connection structure is arranged outside the interconnect system.

36. The apparatus of claim 32, wherein the electrical interconnect system has a plurality of metallization levels and at least one via connection between connecting regions of two metallization levels, and the electrical connection structure has a via connection and/or a contact between a via connection and a connecting region and/or another electrical connection.

37. The apparatus of claim 32, wherein the electrical connection elements contained in the electrical connection structure are produced in the same way and/or together with structurally identical electrical connection elements of the electrical interconnect system.