Frequency synthesizer using two phase locked loops

• US 20080197891A1
• Filed: 09/20/2007
• Published: 08/21/2008
• Est. Priority Date: 09/21/2006
• Status: Active Grant

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Lee, Jeong-Woo, Lee, Kyeongho, Park, Joonbae, Koo, Yido
• Granted Patent: US 7,560,960 B2
• Time in Patent Office: Days
• US Class Current: 327/105
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

Claims

1. A frequency synthesizer, comprising:

an integer-N phase locked loop to receive a signal having a reference frequency to output a signal having a first output frequency;

a fractional-N phase locked loop to receive the signal having the reference frequency to output a signal having a second output frequency; and

a circuit to combine the signal having the first output frequency and the signal having the second output frequency to output a signal having an output frequency of the frequency synthesizer.

2. The frequency synthesizer of claim 1, wherein the second output frequency is lower than the first output frequency.

3. The frequency synthesizer of claim 1, wherein a channel spacing of the second output frequency is narrower than that of the first output frequency.

4. The frequency synthesizer of claim 1, wherein the integer-N phase locked loop comprises:

a phase detector to output a voltage corresponding to a phase difference between the signal having the reference frequency and a divided output signal;

a low pass filter to reduce a high frequency component of the voltage output by the phase detector;

a voltage controlled oscillator to output the signal having the first output frequency corresponding to a voltage output by the low pass filter; and

a frequency divider to divide the first output frequency by N, where N is an integer, and to output the divided output signal.

5. The frequency synthesizer of claim 4, wherein the fractional-N phase locked loop comprises:

a second phase detector to output a voltage corresponding to a phase difference between the signal having the reference frequency and a second divided signal;

a second low pass filter to receive the voltage output by the second phase detector and to remove a high frequency component thereof;

a second voltage controlled oscillator to output the signal having the second output frequency corresponding to the voltage output by the second low pass filter; and

a dual-modulus prescaler to divide the second output frequency by M and (M+1) in a predetermined ratio to output the second divided signal, where M is an integer, and wherein N, M and the predetermined ratio are programmable.

6. The frequency synthesizer of claim 1, wherein the fractional-N phase locked loop comprises a sigma-delta modulation type fractional-N phase locked loop.

7. The frequency synthesizer of claim 1, wherein the fractional-N phase locked loop comprises:

a phase detector to output a voltage corresponding to a phase difference between the signal having the reference frequency and a second divided signal;

a low pass filter to receive a voltage output by the phase detector and to remove a high frequency component thereof;

a voltage controlled oscillator to output the signal having the second output frequency corresponding to the voltage output by the low pass filter; and

a dual-modulus prescaler to divide the second output frequency by M and (M+1) in a predetermined ratio to output the second divided signal, where M is an integer.

8. The frequency synthesizer of claim 7, wherein the predetermined ratio is determined by selecting one of M and (M+1) according to a pseudorandom number outputted by the sigma-delta modulator, and wherein M and the predetermined ratio are programmable.

9. The frequency synthesizer of claim 1, wherein the circuit comprises a frequency adder to receive the signal having the first output frequency and the signal having the second output frequency to output the signal having the output frequency corresponding to a sum of the first output frequency and the second output frequency.

10. The frequency synthesizer of claim 9, wherein the frequency adder comprises:

a mixer to output a signal obtained by multiplying the signal having the first output frequency and the signal having the second output frequency; and

a filter to selectively output a signal in a prescribed band of the signal outputted by the mixer.

11. The frequency synthesizer of claim 9, wherein the signal having the first output frequency comprises an in-phase signal having the first output frequency and a quadrature signal having the first output frequency, wherein the signal having the second output frequency comprises an in-phase signal having the second output frequency and a quadrature signal having the second output frequency, and wherein the frequency adder comprises:

a first mixer to output a signal obtained by multiplying the in-phase signal having the first output frequency and the in-phase signal having the second output frequency;

a second mixer to output a signal obtained by multiplying the quadrature signal having the first output frequency and the quadrature signal having the second output frequency; and

an adder to output a signal obtained by adding the signal outputted by the first mixer and the signal outputted by the second mixer

14. The frequency synthesizer of claim 11, wherein the integer-N phase locked loop comprises:

a phase detector to output a voltage corresponding to a phase difference between the reference frequency signal and a divided output signal;

a low pass filter to reduce a high frequency component of the voltage output by the phase detector;

a voltage controlled oscillator to output the signal having the first output frequency corresponding to a voltage output by the low pass filter; and

a frequency divider to divide the first output frequency by N, where N is an integer, and to output the divided output signal.

15. The frequency synthesizer of claim 14, wherein N is programmable, and wherein the fractional-N phase locked loop comprises a sigma-delta modulation type fractional-N phase locked loop where M is programmable.

12. A frequency synthesizer comprising:

a reference frequency oscillator to output a reference frequency signal;

an integer-N phase locked loop to receive the reference frequency signal to output a signal having a first output frequency;

a fractional-N phase locked loop to receive the reference frequency signal to output a signal having a second output frequency;

a first divider to receive the signal having the second output frequency to output an in-phase signal having a third output frequency corresponding to 1/L of the second output frequency;

a second divider to receive the signal having the second frequency to output a quadrature signal having the third output frequency;

a first frequency adder to receive the signal having the first output frequency and the in-phase signal having the third output frequency to output an in-phase signal having a frequency corresponding to a sum of the first output frequency and the third output frequency; and

a second frequency adder to receive the signal having the first output frequency and the quadrature signal having the third output frequency to output a quadrature signal having the frequency corresponding to the sum of the first output frequency and the third output frequency, wherein L is an integer.

13. The frequency synthesizer of claim 12, wherein the second output frequency is lower than the first output frequency, wherein a channel spacing of the second output frequency is narrower than that of the first output frequency, and wherein L is a multiple of 2.

16. The frequency synthesizer of claim 12, wherein the fractional-N phase locked loop comprises:

a phase detector to output a voltage corresponding to a phase difference between the reference frequency signal and a second divided signal;

a low pass filter to receive the voltage output by the phase detector and to remove a high frequency component thereof;

a voltage controlled oscillator to output the signal having the second output frequency corresponding to the voltage output by the low pass filter; and

a dual-modulus prescaler to divide the second output frequency by M and (M+1) in a predetermined ratio to output the second divided signal, wherein M is an integer.

17. The frequency synthesizer in accordance with claim 16, wherein the predetermined ratio is determined by selecting one of M and (M+1) according to a pseudorandom number outputted by the sigma-delta modulator, and wherein M and the predetermined ratio are programmable.

18. The frequency synthesizer of claim 12, wherein the first frequency adder comprises:

a first mixer to output a signal obtained by multiplying the signal having the first output frequency and the in-phase signal having the third output frequency; and

a first filter to selectively output a signal in a predetermined band selected from of the signal outputted by the first mixer, and wherein the second frequency adder comprises;

a second mixer to output a signal obtained by multiplying the signal having the first output frequency and the quadrature signal having the third output frequency; and

a second filter to selectively output the signal in the predetermined band selected from the signal outputted by the second mixer.