Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling
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Abstract
A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.
35 Citations
42 Claims
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1-22. -22. (canceled)
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23. A receiver structure comprising:
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an input buffer comprising a differential pair of transistors and a first supply voltage, the differential pair of transistors adapted to receive a pair of differential inputs and generate a pair of differential outputs; and a level shifter to receive the pair of differential outputs and to provide gain to the pair of differential outputs to form a gained pair of differential outputs, the level shifter comprising a second supply voltage having a smaller magnitude than the first supply voltage. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A method for processing a pair of differential inputs, the method comprising:
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receiving the pair of differential inputs; buffering the pair of differential inputs using a plurality of transistors of a first oxide thickness to produce a pair of differential outputs; and level shifting the pair of differential outputs using a plurality of transistors of a second oxide thickness to provide gain to the pair of differential outputs and to form a gained pair of differential outputs, wherein the second oxide thickness is less than the first oxide thickness. - View Dependent Claims (36, 37, 38, 39)
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40. A receiver structure comprising:
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an input buffer that receives an adapted pair of inputs and that produces a differential pair of outputs; and a level shifter that is coupled to receive the differential pair of outputs and that provides gain to the differential pair of outputs to form a gained pair of outputs, wherein the input buffer is supplied by a first supply voltage and the level shifter is supplied by a second supply voltage, the first supply voltage having a greater magnitude than the second supply voltage. - View Dependent Claims (41, 42)
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Specification