Reduced edge effect from recesses in imagers

• US 20080198248A1
• Filed: 02/20/2007
• Published: 08/21/2008
• Est. Priority Date: 02/20/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Saijin
• Granted Patent: US 7,952,155 B2
• Time in Patent Office: Days
• US Class Current: 348/273
• CPC Class Codes: G02B 3/0056 arranged along two different directions in a plane, e.g. honeycomb arrangement of lenses G02B3/0043 takes precedence; miniaturised objectives for electronic devices employing wafer level optics G02B13/0085
• CPC Class Codes: G02B 5/201 in the form of arrays

Abstract

Methods for making a recessed color filter array for a semiconductor imager employing a sidewall spacer for reducing an edge effect from the array are disclosed. In one embodiment, a substrate is provided having an upper surface. Then, a recess is formed into the upper surface of the substrate. The recess has a bottom and a sidewall. Subsequently, a sidewall spacer is formed on the sidewall of the recess. A color resist is deposited into the recess after forming the sidewall spacer. In the embodiment, the sidewall spacer is formed of a material having a surface energy lower than that of a material defining the bottom of the recess. The color resist, when deposited into the recess, adheres less to the sidewall than to the bottom of the recess. Thus, the color resist does not conform to a shape of an edge portion of the recess where the sidewall and the bottom meet, thereby reducing the edge effect.

Claims

1. A method of making a semiconductor imaging device, the method comprising:

providing a substrate having an upper surface;

forming a recess into the upper surface of the substrate, the recess having a bottom and a sidewall;

forming a sidewall spacer on the sidewall of the recess; and

forming a color filter layer within the recess after forming the sidewall spacer.

2. The method of claim 1, wherein providing the substrate comprises depositing a first material, the first material having a first surface energy;

wherein forming the recess comprises removing a portion of the first material so as to define the recess; and

wherein forming the sidewall spacer comprises forming the sidewall spacer with a second material having a second surface energy lower than the first surface energy.

3. The method of claim 2, wherein the first surface energy is from about 55 dynes/cm² to about 65 dynes/cm².

4. The method of claim 3, wherein the second surface energy is from about 12 dynes/cm² to about 30 dynes/cm².

5. The method of claim 1, wherein forming the sidewall spacer comprises depositing a hydrophobic material.

6. The method of claim 5, wherein depositing the hydrophobic material comprises depositing a self-assembled monolayer material.

7. The method of claim 6, wherein depositing the self-assembled monolayer material comprises depositing a fluorinated self-assembled monolayer material.

8. The method of claim 7, wherein depositing the fluorinated self-assembled monolayer material comprises depositing 1H,1H,2H,2H-perfluorodecyltrichlorosilane (FDTS).

9. The method of claim 1, wherein forming the color filter layer comprises depositing a color resist into the recess.

10. The method of claim 9, wherein the color resist comprises at least one of propylene glycol monomethyl ether acetate (PGMEA), ethyl 3-ethoxypropionate (EEP), cyclohexanone and acrylic resin.

11. The method of claim 1, wherein forming the recess comprises:

etching the substrate so as to define the recess; and

forming a liner layer at least on the bottom of the recess.

12. The method of claim 11, wherein forming the liner layer comprises depositing a dielectric material.

13. The method of claim 12, wherein depositing the dielectric material comprises depositing silicon nitride (Si₃N₄).

14. The method of claim 1, wherein providing the substrate further comprises forming photodiodes in the substrate such that the photodiodes are positioned under the bottom of the recess.

15. The method of claim 1, wherein providing the substrate further comprises forming at least one conductive line such that the conductive line is positioned lateral to the sidewall of the recess.

16. The method of claim 1, wherein forming the sidewall spacer comprises:

depositing a spacer material at least on the bottom and sidewall of the recess; and

removing the spacer material from the bottom of the recess while leaving the spacer material on the sidewall of the recess.

17. The method of claim 16, wherein depositing the spacer material comprises conformally depositing the spacer material over the bottom and sidewall of the recess.

18. The method of claim 16, wherein removing the spacer material comprises anisotropically etching the spacer material.

19. The method of claim 16, wherein removing the spacer material comprises using a reactive ion etching (RIE) process.

20. The method of claim 1, further comprising, prior to forming the sidewall spacer, forming a reentrant profile on the sidewall of the recess.

21. The method of claim 20, wherein forming the sidewall spacer comprises depositing a spacer material so as to at least partially cover the reentrant profile.

22. The method of claim 20, wherein forming the reentrant profile comprises forming a horizontal protrusion extending over the recess.

23. The method of claim 22, wherein forming the protrusion comprises:

forming a hard mask layer on the surface of the substrate prior to forming the recess; and

etching a portion of the hard mask layer and a portion of the substrate underlying the portion of the hard mask layer so as to form an intermediate recess; and

isotropically etching the substrate so as to expand the intermediate recess while leaving the hard mask layer so as to extend partially over the recess, thereby forming the protrusion.

24. The method of claim 20, further comprising forming a liner layer conformally on the bottom and sidewall of the recess and on the protrusion, prior to forming the sidewall spacer.

25. The method of claim 1, further comprising, prior to forming the sidewall spacer, forming a substantially vertical protrusion at or near an edge of the recess where the sidewall of the recess meets an upper surface of the substrate.

26. The method of claim 25, further comprising, prior to forming the protrusion, forming a liner layer conformally on the bottom and sidewall of the recess, wherein forming the protrusion comprises forming the protrusion on the liner layer.

27. A method of making a CMOS imager, the method comprising:

providing a substrate having an upper surface and a recess formed into the upper surface, the recess having a bottom and a sidewall;

forming a liner layer at least on the bottom of the recess, wherein the liner layer is formed of a first material having a first surface energy; and

treating the sidewall of the recess so as to have a second surface energy lower than the first surface energy.

28. The method of claim 27, further comprising depositing a color filter material into the recess after treating the sidewall, wherein the color filter material has a third surface energy greater than the second surface energy.

29. A semiconductor imaging device comprising:

a substrate having an upper surface, the substrate including a recess formed into the upper surface, the recess including a bottom and a sidewall;

a sidewall spacer formed on the sidewall of the recess; and

an array of color filters formed on the bottom of the recess.

30. The device of claim 29, wherein the bottom of the recess includes a first material having a first surface energy, and wherein the spacer is formed of a second material having a second surface energy lower than the first surface energy.

31. The device of claim 30, wherein the first surface energy is from about 55 dynes/cm² to about 65 dynes/cm².

32. The device of claim 30, wherein the second surface energy is not greater than about 40 dynes/cm².

33. The device of claim 30, wherein the color filters are formed of a color resist having a third surface energy greater than the second surface energy.

34. The device of claim 33, wherein the color resist comprises at least one of propylene glycol monomethyl ether acetate (PGMEA), ethyl 3-ethoxypropionate (EEP), cyclohexanone and acrylic resin.

35. The device of claim 29, wherein the bottom of the recess is defined by a dielectric material.

36. The device of claim 35, wherein the dielectric material comprises silicon nitride (Si₃N₄).

37. The device of claim 29, wherein the spacer is formed of an organic material.

38. The device of claim 37, wherein the organic material comprises a self-assembled monolayer material.

39. The device of claim 38, wherein the self-assembled monolayer material comprises a fluorinated self-assembled monolayer material.

40. The device of claim 39, wherein the fluorinated self-assembled monolayer material comprises 1H,1H,2H,2H-perfluorodecyltrichlorosilane (FDTS).

41. The device of claim 29, further comprising a passivation layer on the bottom of the recess.

42. The device of claim 41, wherein the passivation layer is formed of silicon nitride (Si₃N₄).

43. The device of claim 41, wherein the passivation layer further comprises a portion interposed between the spacer and the sidewall of the recess.

44. The device of claim 29, further comprising a protrusion extending from an edge of the recess where the sidewall of the recess meets an upper surface of the substrate.

45. The device of claim 44, wherein the protrusion extends substantially horizontally over the recess.

46. The device of claim 44, wherein the protrusion extends substantially vertically.

47. The device of claim 44, wherein the sidewall spacer further comprises a portion at least partially covering the protrusion.

48. The device of claim 47, further comprising a passivation layer interposed between the protrusion and the portion of the spacer.

49. The device of claim 29, further comprising a plurality of photodiodes embedded in the substrate under the bottom of the recess.

50. The device of claim 29, further comprising one or more conductive lines embedded in the substrate, the conductive lines being positioned lateral to the recess.

51. The device of claim 29, wherein the recess has a depth from about 1 μ

m to about 3 μ

m.

52. The device of claim 29, wherein the substrate has no more than one recess.