Distortion Estimation And Cancellation In Memory Devices

• US 20080198650A1
• Filed: 05/10/2007
• Published: 08/21/2008
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Gurgi, Eyal, Sommer, Naftali, Maislos, Ariel
• Granted Patent: US 8,050,086 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

Claims

1. A method for operating a memory, comprising:

storing data in a group of analog memory cells of the memory as respective first voltage levels, selected from a set of possible values;

after storing the data, reading from the analog memory cells respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels;

processing the second voltage levels to derive respective hard decisions, each corresponding to a respective value among the possible values of the first voltage levels;

estimating cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, based on the second voltage levels and the respective hard decisions; and

reconstructing the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.

2. The method according to claim 1, wherein estimating the cross-coupling coefficients comprises processing the second voltage levels and the respective hard decisions using a block estimation process.

3. The method according to claim 1, wherein estimating the cross-coupling coefficients comprises sequentially scanning the second voltage levels and the respective hard decisions using a sequential estimation process that converges to the cross-coupling coefficients.

4. The method according to claim 1, wherein estimating the cross-coupling coefficients comprises applying an estimation process that reduces a distance metric between the read second voltage levels and the respective hard decisions.

5. The method according to claim 1, and comprising evaluating the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

6. The method according to claim 1, wherein reconstructing the data comprises removing the cross-coupling interference from the second voltage levels using one of a linear equalization process, a Decision-Feedback Equalization (DFE) process, a Maximum a Posteriori (MAP) estimation process and a Maximum-Likelihood Sequence Estimation (MLSE) process.

7. The method according to claim 1, wherein estimating the cross-coupling coefficients and reconstructing the data comprise estimating the cross-coupling coefficients in a first processing stage, and canceling the estimated cross-coupling interference in a second processing stage subsequent to the first processing stage.

8. The method according to claim 7, wherein estimating the cross-coupling coefficients and reconstructing the data comprise using the estimated cross-coupling coefficients for subsequent instances of the second processing stage, and repeating the first processing stage only upon failure to reconstruct the data.

9. The method according to claim 1, wherein storing the data comprises encoding the data using an Error Correcting Code (ECC), wherein reconstructing the data comprises computing error correction metrics based on the estimated cross-coupling coefficients and decoding the ECC using the error correction metrics.

10. A method for operating a memory, comprising:

storing data as respective first voltage levels in analog memory cells of the memory, in which a subset of the memory cells has correlative distortion;

after storing the data, reading from one or more of the analog memory cells in the subset respective second voltage levels, which differ from the first voltage levels due to the correlative distortion;

processing the second voltage levels read from the one or more of the analog memory cells in order to estimate respective distortion levels in the second voltage levels;

reading a second voltage level from another analog memory cell in the subset;

predicting a distortion level in the second voltage level read from the other analog memory cell based on the estimated respective distortion levels of the one or more of the analog memory cells in the subset;

correcting the second voltage level read from the other memory cell using the predicted distortion level; and

reconstructing the data stored in the other memory cell based on the corrected second voltage level.

11. The method according to claim 10, wherein the subset of the memory cells comprises at least one subset type selected from a group of subset types consisting of memory cells located on a common bit line, memory cells located on a common word line, memory cells having common circuitry and memory cells located in proximity to one another.

12. The method according to claim 10, wherein processing the second voltage levels comprises caching only a single value indicative of the distortion levels in the second voltage levels read from the one or more of the analog memory cells in the subset, and wherein predicting the distortion level comprises calculating the predicted distortion level based on the cached single value.

13. The method according to claim 10, wherein predicting the distortion comprises tracking distortion parameters common to the subset of the memory cells and storing the distortion parameters in a data structure.

14. A method for operating a memory, comprising:

storing data as respective first voltage levels in a group of analog memory cells of the memory;

performing a memory access operation on a first analog memory cell in the memory;

responsively to performing the memory access operation, reading a second voltage level from a second analog memory cell in the memory;

processing the second voltage level so as to estimate a level of disturbance in the second voltage level that was caused by performing the memory access operation on the first analog memory cell;

correcting the second voltage level using the estimated level of the disturbance; and

reconstructing the data stored in the second analog memory cell based on the corrected second voltage level.

15. The method according to claim 14, wherein the memory access operation comprises at least one operation selected from a group of operations consisting of a programming operation, a reading operation and an erasure operation.

16. The method according to claim 14, wherein processing and correcting the second voltage level comprise comparing the estimated level of the disturbance to a predefined level, and correcting the second voltage level only when the estimated level of the disturbance exceeds the predefined level.

17. The method according to claim 14, wherein correcting the second voltage level comprises re-programming the data stored in the second analog memory cell.

18. The method according to claim 14, wherein correcting the second voltage level comprises copying the data stored in the second analog memory cell to another analog memory cell different from the second analog memory cell.

19. The method according to claim 14, wherein correcting the second voltage level comprises increasing a first voltage level used for storing the data in the second memory cell.

20. The method according to claim 14, wherein processing the second voltage level is performed during idle periods when not storing and reading the data.

21. The method according to claim 14, wherein reading the second voltage level comprises reading multiple second voltage levels from respective multiple second memory cells, and wherein processing the second voltage levels comprises assessing a number of the second memory cells that transitioned from an erased level to a programmed level due to the memory access operation.

22. The method according to claim 14, wherein storing the data comprises storing the data in sequential order in multiple groups of the analog memory cells, wherein reading the second voltage level comprises reading the groups of the memory cells in reverse order, and wherein processing the second voltage level comprises estimating the level of the disturbance caused to the first memory cell responsively to the second voltages of the memory cells in the groups that were read before the first memory cell.

23. A method for operating a memory, comprising:

storing data as respective first voltage levels in a group of analog memory cells of the memory;

after storing the data, reading from the analog memory cells respective second voltage levels, at least some of which differ from the respective first voltage levels;

identifying a subset of the analog memory cells that potentially cause distortions to a second voltage level read from a target analog memory cell;

classifying the analog memory cells in the subset into multiple classes based on a relation between respective times at which the data was stored in the analog memory cells and a time at which the data was stored in the target analog memory cell;

estimating, for each of the classes, a respective distortion caused to the second voltage level in the target memory cell by the analog memory cells in the class;

correcting the second voltage level read from the target analog memory cell using the estimated respective distortion for each of one or more of the classes; and

reconstructing the data stored in the target analog memory cell based on the corrected second voltage level.

24. The method according to claim 23, wherein storing the data and reading the second voltage levels comprise applying a Program and Verify (P&

V) process.

25. The method according to claim 23, wherein classifying the analog memory cells comprises identifying the analog memory cells in the subset in which the data was stored more recently than in the target analog memory cell, and wherein correcting the second voltage level comprises correcting the second voltage level read from the target analog memory cell based on the distortion in only the identified analog memory cells.

26. The method according to claim 23, wherein classifying the analog memory cells comprises defining a first class comprising the analog memory cells in the subset in which the data was stored more recently than in the target analog memory cell, a second class comprising the analog memory cells in the subset in which the data was stored earlier than in the target analog memory cell, and a third class comprising the analog memory cells in the subset in which the data was stored concurrently with storing the data in the target analog memory cell.

27. The method according to claim 23, wherein reading the second voltage levels, estimating the distortion and correcting the second voltage level comprise processing the second voltage level read from the target analog memory cell with a first resolution and processing the second voltage levels read from the analog memory cells in the subset with a second resolution coarser than the first resolution.

28. The method according to claim 23, wherein storing the data comprises storing indications of the times at which the data was stored in the analog memory cells, and wherein classifying the analog memory cells comprises querying the stored indications.

29. The method according to claim 23, wherein estimating the distortion comprises estimating a level of the distortion responsively to at least one parameter selected from a group of parameters consisting of programming times of the analog memory cells, the data stored in the analog memory cells, a location of the analog memory cells with respect to the target memory cell and a number of recent programming-erasure cycles the target memory cell has gone through.

30. A method for operating a memory, comprising:

accepting data for storage in the memory;

determining respective first voltage levels for programming a group of analog memory cells of the memory so as to cause the analog memory cells to store respective values of a physical quantity that represent the data;

programming the analog memory cells in the group using the determined first voltage levels;

after programming the analog memory cells, reading second voltage levels from the respective analog memory cells and reconstructing the data from the second voltage levels.

31. The method according to claim 30, wherein determining the first voltage levels comprises estimating distortion caused to a value of the physical quantity stored in a target analog memory cell by the values of the physical quantities stored in one or more other analog memory cells when storing the data in the target analog memory cell, and pre-correcting a first voltage level used for programming the target analog memory cell responsively to the estimated distortion.

32. The method according to claim 30, wherein reconstructing the data comprises estimating distortion caused to a value of the physical quantity stored in a target analog memory cell by the values of the physical quantities stored in one or more other analog memory cells when reading the second voltage levels based on the read second voltage levels, correcting a second voltage level read from the target analog memory cell using the estimated distortion, and reconstructing the data stored in the target analog memory cell based on the corrected second voltage level.

33. The method according to claim 30, wherein programming the analog memory cells comprises verifying the programmed first voltage levels.

34. The method according to claim 30, wherein the physical quantity comprises an electrical charge.

35. A method for operating a memory, comprising:

storing data as respective first voltage levels in a group of analog memory cells of the memory;

after storing the data, reading from the analog memory cells in the group second voltage levels, at least some of which differ from the respective first voltage levels;

estimating a distortion level in the second voltage levels read from the analog memory cells; and

when the estimated distortion level violates a predetermined distortion criterion, re-programming the data into the analog memory cells of the memory.

36. The method according to claim 35, wherein the predetermined distortion criterion comprises a threshold defining a maximum tolerable distortion level.

37. A method for operating a memory, comprising:

storing data as respective first voltage levels in a group of analog memory cells of the memory;

after storing the data, reading from the analog memory cells respective second voltage levels, at least some of which differ from the respective first voltage levels;

identifying a subset of the analog memory cells that potentially cause distortions to a second voltage level read from a target analog memory cell;

estimating a difference between a first distortion level caused by the memory cells in the subset to the target memory cell at a first time instant in which the target memory cell was programmed and a second distortion level caused by the memory cells in the subset to the target memory cell at a second time instant in which the target memory cell was read; and

correcting the second voltage level read from the target memory cell using the estimated difference.

38. A method for operating a memory, comprising:

storing data in a group of analog memory cells of the memory as respective first voltage levels;

after storing the data, reading from the analog memory cells respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels;

estimating cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells by processing the second voltage levels; and

reconstructing the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.

39. The method according to claim 38, and comprising evaluating the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

40. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data in a group of the analog memory cells as respective first voltage levels selected from a set of possible values, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to process the second voltage levels to derive respective hard decisions, each corresponding to a respective value among the possible values of the first voltage levels, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, based on the second voltage levels and the respective hard decisions, and to reconstruct the data stored in the group of analog memory cells from the second voltage levels using the estimated cross-coupling coefficients.

41. The apparatus according to claim 40, wherein the MSP is arranged to estimate the cross-coupling coefficients comprises by processing the second voltage levels and the respective hard decisions using a block estimation process.

42. The apparatus according to claim 40, wherein the MSP is arranged to estimate the cross-coupling coefficients by sequentially scanning the second voltage levels and the respective hard decisions using a sequential estimation process that converges to the cross-coupling coefficients.

43. The apparatus according to claim 40, wherein the MSP is arranged to apply an estimation process that reduces a distance metric between the read second voltage levels and the respective hard decisions.

44. The apparatus according to claim 40, wherein the MSP is arranged to evaluate the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

45. The apparatus according to claim 40, wherein the MSP is arranged to remove the cross-coupling interference from the second voltage levels using one of a linear equalization process, a Decision-Feedback Equalization (DFE) process, a Maximum a Posteriori (MAP) estimation process and a Maximum-Likelihood Sequence Estimation (MLSE) process.

46. The apparatus according to claim 40, wherein the MSP is arranged to estimate the cross-coupling coefficients in a first processing stage, and to cancel the estimated cross-coupling interference in a second processing stage subsequent to the first processing stage.

47. The apparatus according to claim 46, wherein the MSP is arranged to use the estimated cross-coupling coefficients for subsequent instances of the second processing stage, and to repeat the first processing stage only upon failure to reconstruct the data.

48. The apparatus according to claim 40, wherein the MSP is arranged to encode the data using an Error Correcting Code (ECC) before storing the data, to compute error correction metrics based on the estimated cross-coupling coefficients and to reconstruct the data by decoding the ECC using the error correction metrics.

49. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes multiple analog memory cells, of which a subset of the memory cells has correlative distortion; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data as respective first voltage levels in the analog memory cells, to read from one or more of the analog memory cells in the subset, after storing the data, respective second voltage levels, which differ from the first voltage levels due to the correlative distortion, to process the second voltage levels read from the one or more of the analog memory cells in order to estimate respective distortion levels in the second voltage levels, to read a second voltage level from another analog memory cell in the subset, to predict a distortion level in the second voltage level read from the other analog memory cell based on the estimated respective distortion levels of the one or more of the analog memory cells in the subset, to correct the second voltage level read from the other memory cell using the predicted distortion level, and to reconstruct the data stored in the other memory cell based on the corrected second voltage level.

50. The apparatus according to claim 49, wherein the subset of the memory cells comprises at least one subset type selected from a group of subset types consisting of memory cells located on a common bit line, memory cells located on a common word line, memory cells having common circuitry and memory cells located in proximity to one another.

51. The apparatus according to claim 49, wherein the MSP is arranged to cache only a single value indicative of the distortion levels in the second voltage levels read from the one or more of the analog memory cells in the subset, and to calculate the predicted distortion level based on the cached single value.

52. The apparatus according to claim 49, wherein the MSP is arranged to track distortion parameters common to the subset of the memory cells and to store the distortion parameters in a data structure.

53. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to perform a memory access operation on a first analog memory cell in the memory, to read, responsively to performing the memory access operation, a second voltage level from a second analog memory cell in the memory, to process the second voltage level so as to estimate a level of disturbance in the second voltage level that was caused by performing the memory access operation on the first analog memory cell, to correct the second voltage level using the estimated level of the disturbance, and to reconstruct the data stored in the second analog memory cell based on the corrected second voltage level.

54. The apparatus according to claim 53, wherein the memory access operation comprises at least one operation selected from a group of operations consisting of a programming operation, a reading operation and an erasure operation.

55. The apparatus according to claim 53, wherein the MSP is arranged to compare the estimated level of the disturbance to a predefined level, and to correct the second voltage level only when the estimated level of the disturbance exceeds the predefined level.

56. The apparatus according to claim 53, wherein the MSP is arranged to correct the second voltage level by re-programming the data stored in the second analog memory cell.

57. The apparatus according to claim 53, wherein the MSP is arranged to copy the data stored in the second analog memory cell to another analog memory cell different from the second analog memory cell.

58. The apparatus according to claim 53, wherein the MSP is arranged to increase a first voltage level used for storing the data in the second memory cell.

59. The apparatus according to claim 53, wherein the MSP is arranged to process the second voltage level during idle periods when not storing and reading the data.

60. The apparatus according to claim 53, wherein the MSP is arranged to read multiple second voltage levels from respective multiple second memory cells, and to assess a number of the second memory cells that transitioned from an erased level to a programmed level due to the memory access operation.

61. The apparatus according to claim 53, wherein the MSP is arranged to store the data in sequential order in multiple groups of the analog memory cells, to read the groups of the memory cells in reverse order, and to estimate the level of the disturbance caused to the first memory cell responsively to the second voltages of the memory cells in the groups that were read before the first memory cell.

62. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to read from the analog memory cells, after storing the data, respective second voltage levels, at least some of which differ from the respective first voltage levels, to identify a subset of the analog memory cells that potentially cause distortions to a second voltage level read from a target analog memory cell, to classify the analog memory cells in the subset into multiple classes based on a relation between respective times at which the data was stored in the analog memory cells and a time at which the data was stored in the target analog memory cell, to estimate, for each of the classes, a respective distortion caused to the second voltage level in the target memory cell by the analog memory cells in the class, to correct the second voltage level read from the target analog memory cell using the estimated respective distortion for each of one or more of the classes, and to reconstruct the data stored in the target analog memory cell based on the corrected second voltage level.

63. The apparatus according to claim 62, wherein the MSP is arranged to store the data and read the second voltage levels by applying a Program and Verify (P&

V) process.

64. The apparatus according to claim 62, wherein the MSP is arranged to identify the analog memory cells in the subset in which the data was stored more recently than in the target analog memory cell, and to correct the second voltage level read from the target analog memory cell based on the distortion in only the identified analog memory cells.

65. The apparatus according to claim 62, wherein the MSP is arranged to define a first class comprising the analog memory cells in the subset in which the data was stored more recently than in the target analog memory cell, a second class comprising the analog memory cells in the subset in which the data was stored earlier than in the target analog memory cell, and a third class comprising the analog memory cells in the subset in which the data was stored concurrently with storing the data in the target analog memory cell.

66. The apparatus according to claim 62, wherein the MSP is arranged to process the second voltage level read from the target analog memory cell with a first resolution, and to process the second voltage levels read from the analog memory cells in the subset with a second resolution coarser than the first resolution.

67. The apparatus according to claim 62, wherein the MSP is arranged to store indications of the times at which the data was stored in the analog memory cells when storing the data, and to query the stored indications in order to classify the analog memory cells.

68. The apparatus according to claim 62, wherein the MSP is arranged to estimate the distortion responsively to at least one parameter selected from a group of parameters consisting of programming times of the analog memory cells, the data stored in the analog memory cells, a location of the analog memory cells with respect to the target memory cell and a number of recent programming-erasure cycles the target memory cell has gone through.

69. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to accept data for storage in the memory, to determine respective first voltage levels for programming a group of the analog memory cells so as to cause the analog memory cells to store respective values of a physical quantity that represent the data, to program the analog memory cells in the group using the first voltage levels, to read, after programming the analog memory cells, second voltage levels from the respective analog memory cells, and to reconstruct the data from the second voltage levels.

70. The apparatus according to claim 69, wherein the MSP is arranged to estimate distortion caused to a value of the physical quantity stored in a target analog memory cell by the values of the physical quantities stored in one or more other analog memory cells when storing the data in the target analog memory cell, and to pre-correct a first voltage level used for programming the target analog memory cell responsively to the estimated distortion.

71. The apparatus according to claim 69, wherein the MSP is arranged to estimate distortion caused to a value of the physical quantity stored in a target analog memory cell by the values of the physical quantities stored in one or more other analog memory cells when reading the second voltage levels based on the read second voltage levels, to correct a second voltage level read from the target analog memory cell using the estimated distortion, and to reconstruct the data stored in the target analog memory cell based on the corrected second voltage level.

72. The apparatus according to claim 69, wherein the MSP is arranged to verify the programmed first voltage levels when programming the respective analog memory cells.

73. The apparatus according to claim 69, wherein the physical quantity comprises an electrical charge.

74. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to read from the analog memory cells in the group, after storing the data, second voltage levels, at least some of which differ from the respective first voltage levels, to estimate a distortion level in the second voltage levels read from the analog memory cells, and, when the estimated distortion level violates a predetermined distortion criterion, to re-program the data into the analog memory cells in the group.

75. The apparatus according to claim 74, wherein the predetermined distortion criterion comprises a threshold defining a maximum tolerable distortion level.

76. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data as respective first voltage levels in a group of the analog memory cells of the memory, to read from the analog memory cells, after storing the data, respective second voltage levels, at least some of which differ from the respective first voltage levels, to identify a subset of the analog memory cells that potentially cause distortions to a second voltage level read from a target analog memory cell, to estimate a difference between a first distortion level caused by the memory cells in the subset to the target memory cell at a first time instant in which the target memory cell was programmed and a second distortion level caused by the memory cells in the subset to the target memory cell at a second time instant in which the target memory cell was read, and to correct the second voltage level read from the target memory cell using the estimated difference.

77. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data in a group of the analog memory cells of the memory as respective first voltage levels, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells by processing the second voltage levels, and to reconstruct the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.

78. The apparatus according to claim 77, wherein the MSP is arranged to evaluate the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

79. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data in a group of the analog memory cells as respective first voltage levels selected from a set of possible values, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to process the second voltage levels to derive respective hard decisions, each corresponding to a respective value among the possible values of the first voltage levels, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, based on the second voltage levels and the respective hard decisions, and to reconstruct the data stored in the group of analog memory cells from the second voltage levels using the cross-coupling coefficients.

80. A data storage apparatus, comprising:

a memory, which comprises multiple analog memory cells, of which a subset of the memory cells has correlative distortion; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to read from one or more of the analog memory cells in a column of the array, after storing the data, respective second voltage levels, which differ from the first voltage levels due to a distortion, to process the second voltage levels read from the one or more of the analog memory cells in order to estimate respective distortion levels in the second voltage levels, to read a second voltage level from another analog memory cell in the column, to predict a distortion level in the second voltage level read from the other analog memory cell based on the estimated respective distortion levels of the one or more of the analog memory cells in the column, to correct the second voltage level read from the other memory cell using the predicted distortion level, and to reconstruct the data stored in the other memory cell based on the corrected second voltage level.

81. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to perform a memory access operation on a first analog memory cell in the memory, to read, responsively to performing the memory access operation, a second voltage level from a second analog memory cell in the memory, to process the second voltage level so as to estimate a level of disturbance in the second voltage level that was caused by performing the memory access operation on the first analog memory cell, to correct the second voltage level using the estimated level of the disturbance, and to reconstruct the data stored in the second analog memory cell based on the corrected second voltage level.

82. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to read from the analog memory cells, after storing the data, respective second voltage levels, at least some of which differ from the respective first voltage levels, to identify a subset of the analog memory cells that potentially cause distortions to a second voltage level read from a target analog memory cell, to classify the analog memory cells in the subset into multiple classes based on a relation between respective times at which the data was stored in the analog memory cells and a time at which the data was stored in the target analog memory cell, to estimate, for each of the classes, a respective distortion caused to the second voltage level in the target memory cell by the analog memory cells in the class, to correct the second voltage level read from the target analog memory cell using the estimated respective distortion for each of one or more of the classes, and to reconstruct the data stored in the target analog memory cell based on the corrected second voltage level.

83. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to accept data for storage in the memory, to determine respective first voltage levels for programming a group of the analog memory cells so as to cause the analog memory cells to store respective values of a physical quantity that represent the data, to program the analog memory cells in the group using the first voltage levels, to read, after programming the analog memory cells, second voltage levels from the respective analog memory cells, and to reconstruct the data from the second voltage levels.

84. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to read from the analog memory cells in the group, after storing the data, second voltage levels, at least some of which differ from the respective first voltage levels, to estimate a distortion level in the second voltage levels read from the analog memory cells, and, when the estimated distortion level violates a predetermined distortion criterion, to re-program the data into the analog memory cells in the group.

85. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data as respective first voltage levels in a group of the analog memory cells of the memory, to read from the analog memory cells, after storing the data, respective second voltage levels, at least some of which differ from the respective first voltage levels, to identify a subset of the analog memory cells that potentially cause distortions to a second voltage level read from a target analog memory cell, to estimate a difference between a first distortion level caused by the memory cells in the subset to the target memory cell at a first time instant in which the target memory cell was programmed and a second distortion level caused by the memory cells in the subset to the target memory cell at a second time instant in which the target memory cell was read, and to correct the second voltage level read from the target memory cell using the estimated difference.

86. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data in a group of the analog memory cells of the memory as respective first voltage levels, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells by processing the second voltage levels, and to reconstruct the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.