NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION

• US 20080198651A1
• Filed: 07/27/2007
• Published: 08/21/2008
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin-Ki
• Granted Patent: US 7,646,636 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.

Claims

1. A flash memory device having a memory array comprising:

a command decoder for issuing one of a multiple bit per cell (MBC) program command and a single bit per cell (SBC) program command in response to an external program command;

a control logic circuit for executing a programming algorithm in response to either the multiple bit per cell program command or the single bit per cell program command; and

,

flash memory circuitry for programming memory cells of the memory array in response to the programming algorithm.

2. The flash memory device of claim 1, wherein the command decoder includes an SBC command decoder for issuing the SBC program command, and an MBC command decoder for issuing the MBC program command.

3. The flash memory device of claim 1, wherein the memory array includes first subdivisions configured for storing data in an MBC storage mode in response to the MBC program command, and second subdivisions configured for storing data in an SBC storage mode in response to the SBC program command.

4. The flash memory device of claim 3, wherein the first subdivisions and the second subdivisions include memory blocks.

5. The flash memory device of claim 3, wherein the first subdivisions and the second subdivisions include memory pages.

6. The flash memory device of claim 3, wherein each subdivision is associated with a mode tag for designating the MBC storage mode or the SBC storage mode.

7. The flash memory device of claim 6, wherein each subdivision is a memory page in the memory array.

8. A method for storing data in a flash memory device comprising:

a) converting a subdivision of the flash memory device from a first storage mode to a second storage mode, the subdivision having a corresponding mode tag indicative of either the first storage mode and the second storage mode; and

b) programming the data to one of the subdivision and an alternate subdivision.

9. The method of claim 8, wherein the first storage mode is a multiple bit per cell (MBC) storage mode and the second storage mode is a single bit per cell (SBC) storage mode.

10. The method of claim 9, wherein the step of converting is executed in response to a predetermined criteria.

11. The method of claim 10, wherein the predetermined criteria is an MBC program erase limit.

12. The method of claim 11, wherein the step of converting includes comparing a program/erase counter corresponding to the subdivision with the MBC program/erase limit.

13. The method of claim 12, wherein the step of programming includes programming the data to the subdivision if the program/erase counter is less than the predetermined MBC program/erase limit, and programming the data to the alternate subdivision if the program/erase counter is at least the predetermined MBC program/erase limit.

14. The method of claim 13, wherein the step of programming further includes erasing the subdivision if the data is programmed to the alternate subdivision.

15. The method of claim 13, wherein the step of programming further includes setting the mode tag corresponding to the subdivision to a state indicative of the second storage mode.

16. The method of claim 13, wherein the step of programming further includes resetting the program/erase counter.

17. The method of claim 10, wherein the predetermined criteria is a specific profile of the data.

18. The method of claim 17, wherein the specific profile of the data includes a set of data file types.

19. The method of claim 18, wherein the step of programming includes programming the data to the subdivision if the data has a profile matching the specific profile, and programming the data to the alternate subdivision if the profile mismatches the specific profile.

20. The method of claim 8, wherein the subdivision includes a block, the block having a predetermined number of pages.

21. The method of claim 8, wherein the subdivision includes a page, and a predetermined number of the pages are included in a block.

22. The method of claim 8, wherein the first storage mode is a single bit per cell (SBC) storage mode and the second storage mode is a multiple bit per cell (MBC) storage mode.

23. The method of claim 22, wherein the step of converting includes comparing an SBC program/erase counter corresponding to the subdivision to a reclaim limit, and checking a state of a lock bit corresponding to the subdivision if the program/erase counter is less than the reclaim limit.

24. The method of claim 23, wherein the step of converting further includes changing a state of a mode tag corresponding to the subdivision if the state of the lock bit is false.

25. The method of claim 24, wherein the step of converting further includes setting the lock bit to true after the state of the mode tag is changed.

26. A multi-mode flash memory device comprising:

a memory array having flash memory cells for storing single bit per cell (SBC) data in an SBC storage mode and for storing multiple bit per cell (MBC) data in an MBC storage mode.

27. The multi-mode flash memory device of claim 26, wherein a first block of the memory array stores SBC data and a second block of the memory stores MBC data.

28. The multi-mode flash memory device of claim 26, wherein a first page in a block of the memory array stores SBC data and a second page in the block of the memory array stores MBC data.

29. The multi-mode flash memory device of claim 28, wherein the first page and the second page each stores a mode tag, the mode tag having a logic state indicating a presence of SBC data or MBC data.

30. A method for selectively programming data in a flash memory system in one of a multiple bit per cell (MBC) storage mode and a single bit per cell (SBC) storage mode, comprising:

a) receiving data;

b) determining a high reliability level or a low reliability level of the data;

c) programming the data in the SBC storage mode if the data is determined to be high reliability; and

,

d) programming the data in the MBC storage mode if the data is determined to be low reliability.

31. The method for selectively programming data of claim 30, wherein the step of programming the data in the SBC storage mode includes programming the data to selected SBC pages in a memory array of a flash memory device and setting mode tags corresponding to each of the selected SBC pages to a first state.

32. The method for selectively programming data of claim 31, wherein the step of programming the data in the MBC storage mode includes programming the data to selected MBC pages in the memory array of the flash memory device and setting the mode tags corresponding to each of the selected MBC pages to a second state.

33. A method for reading data from a flash memory system having multiple bit per cell (MBC) pages and (SBC) pages, comprising:

a) receiving a read address for reading at least one page of the flash memory array;

b) executing an MBC read operation at the read address if a mode tag corresponding to the at least one page is in a first logic state; and

,

c) executing an SBC read operation at the read address if the mode tag corresponding to the at least one page is in a second logic state.

34. The method for reading data of claim 33, including initializing an address mapping table with mode tags corresponding to each page of the flash memory array prior to receiving the read address.

35. The method for reading data of claim 34, wherein the step of initializing includes

powering up the flash memory array,

reading the mode tags stored in each page of the flash memory array, and

storing the mode tags with logical address entries corresponding to each page of the flash memory array.

36. The method for reading data of claim 35, wherein the step of reading the mode tags includes executing an SBC read operation for reading the mode tags in each page of the flash memory array.

37. The method for reading data of claim 33, wherein the step of receiving includes issuing an external read command from a flash controller to a flash memory device, the external read command being generated in response to the read address and the logic state of the mode tag corresponding to the read address.

38. The method for reading data of claim 37, wherein executing the MBC read operation includes decoding the external read command within the flash memory device and issuing one of an internal MBC read command and an internal SBC read command.