SEMICONDUCTOR MEMORY DEVICE
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Abstract
A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0<L1<L2<L3) being written into the information cell, reference level Lr (where, L0<Lr<L1) being written into the reference cell to used for detecting the data level of the information cell, and wherein the sense amplifier circuit detects a cell current difference between the information cell and the reference cell simultaneously selected from the first and second cell arrays.
80 Citations
18 Claims
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1. (canceled)
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2. :
- A semiconductor memory device comprising;
first and second cell arrays each having a plurality of electrically rewritable memory cells arranged therein; and a sense amplifier circuit configured to read out data of the first and second cell arrays, wherein plural information cells are set in the first cell array, and at least one reference cell are set in the second cell array, one of four data levels L0, L1, L2 and L3 (where, L0<
L1<
L2<
L3) being written into the information cell, reference level Lr (where, L0<
Lr<
L1) being written into the reference cell to be used for detecting the data level of the information cell,wherein the sense amplifier circuit is configured to detect a cell current difference between the information cell and the reference cell selected from the first and second cell arrays, respectively, wherein the four data levels L0, L1, L2 and L3 of the information cell are threshold voltage levels with a relationship as follows; L0 is an erase state with a certain threshold voltage; and L1, L2 and L3 are write states with threshold voltages with a relationship of L1<
L3-L2, and L2-L1<
L3-L2,and wherein the reference level Lr is a write state with a threshold voltage lower than L1. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- A semiconductor memory device comprising;
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13. :
- A semiconductor memory device comprising;
first and second cell arrays each having word lines and bit lines disposed in parallel and a plurality of electrically rewritable memory cells arranged therein, plural information cells and at least one reference cell being set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0<
L1<
L2<
L3) being written into the information cell, a reference level Lr (where, L0<
Lr<
L1) being written into the reference cell to be used for detecting the data level of the information cell;word line driver circuits configured to selectively drive word lines in the first and second cell arrays; and a sense amplifier circuit connected to a pair of bit lines, to which the information cell and the reference cell selected from the first and second cell arrays, are coupled, so as to detect a cell current difference between the information cell and the reference cell, thereby reading out data of the information cell, wherein each of the word line driver circuits has at least two driving modes with respect to driving plural word lines simultaneously selected at a data read time and applied with respectively predetermined word line voltages as follows; a first driving mode for applying a first voltage necessary for data-sensing to a first word line from the beginning; and a second driving mode for applying a third voltage higher than a second voltage necessary for data-sensing to a second word line, and then restoring the third voltage to the second voltage, wherein the four data levels L0, L1, L2 and L3 of the information cell are threshold voltage levels with a relationship as follows; L0 is an erase state with a certain threshold voltage; and L1, L2 and L3 are write states with threshold voltages with a relationship of L1<
L3-L2, and L2-L1<
L3-L2,and wherein the reference level Lr is a write state with a threshold voltage lower than L1. - View Dependent Claims (14, 15, 16, 17, 18)
- A semiconductor memory device comprising;
Specification