Integrated Hydrogen Anneal and Gate Oxidation for Improved Gate Oxide Integrity

• US 20080199995A1
• Filed: 02/15/2007
• Published: 08/21/2008
• Est. Priority Date: 02/15/2007
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Sharp, Joelle, Madson, Gordon K., Olsen, Tony Lane, Woolsey, Debra Susan
• Application Number:
  US11/675,596
• Publication Number:
  US 20080199995A1
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between annealing and forming the dielectric layer, the semiconductor substrate is maintained in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer.

Claims

1. A method for forming a trench gate field effect transistor, comprising:

forming trenches in a semiconductor substrate;

annealing the semiconductor substrate in an ambient including hydrogen gas;

forming a dielectric layer lining at least the sidewalls of the trenches; and

during the time between the annealing and forming the dielectric layer, maintaining the semiconductor substrate in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer.

2. The method of claim 1 wherein the forming a dielectric layer comprises performing an oxidation process to form a gate oxide layer along the sidewalls of the trenches.

3. The method of claim 1 wherein the forming of a dielectric layer comprises performing a nitridation process to form a silicon nitride layer along the sidewalls of the trenches.

4. The method of claim 1 further comprising:

forming an epitaxial layer of a first conductivity type over a drain contact region of the first conductivity type, the epitaxial layer having a higher resistivity than the drain contact region, wherein the trenches extend into and terminate within the epitaxial layer.

5. The method of claim 4 further comprising:

after forming the dielectric layer, forming a gate electrode in each trench;

forming a well region of a second conductivity type in the epitaxial layer;

forming source regions of the first conductivity type in the well region; and

forming heavy body regions of the second conductivity type in the well region.

6. The method of claim 5 further comprising:

prior to forming a gate electrode in each trench, filling a bottom portion of each trench with a thick bottom dielectric, the thick bottom dielectric being thicker than the dielectric layer.

7. The method of claim 1 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 700°

C. to 1200°

C. and at a pressure within a range of about 100 mTorr to 450 Torr.

8. The method of claim 1 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 960°

C. to 1160°

C. and at a pressure within a range of about 40 Torr to 240 Torr.

9. The method of claim 1 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 800°

C. to 1000°

C. and a pressure within the range of about 200 mTorr to 400 mTorr.

10. The method of claim 1 further comprising:

annealing the semiconductor substrate in a first reactor in a hydrogen ambient under reduced pressure;

purging the first reactor to remove the hydrogen gas;

transferring the semiconductor substrate from the first reactor to a second reactor through a transport chamber having an inert ambient; and

forming the dielectric layer in the second reactor in atmospheric pressure.

11. The method of claim 1 further comprising:

annealing the semiconductor substrate in a chamber having a hydrogen ambient under reduced pressure;

purging the chamber to remove the hydrogen gas;

filling the chamber with an inert gas; and

forming the dielectric layer in the chamber under atmospheric pressure.

12. A method for forming a trench gate field effect transistor, comprising:

forming trenches in a semiconductor substrate of a first conductivity type;

annealing the semiconductor substrate in an ambient including hydrogen gas;

performing an oxidation process to form a layer of gate oxide along the sidewalls of the trenches;

during the time between the annealing and performing an oxidation process, maintaining the semiconductor substrate in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the layer of gate oxide;

forming a gate electrode in each trench;

forming a well region of a second conductivity type in the semiconductor substrate;

forming source regions of the first conductivity type in the well region; and

forming heavy body regions of the second conductivity type in the well region.

13. The method of claim 12 wherein the semiconductor substrate comprises an epitaxial layer over a drain contact region, the epitaxial layer having a higher resistivity than the drain contact region, wherein the well region is formed in the epitaxial layer, and the trenches extend through the well region and terminate within the epitaxial layer.

14. The method of claim 12 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 700°

C. to 1200°

C. and at a pressure within a range of about 100 mTorr to 450 Torr.

15. A method of forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor substrate;

forming a shield dielectric layer lining lower sidewalls and bottom of each trench;

forming a shield electrode filling a bottom portion of each trench;

annealing the semiconductor substrate in an ambient including hydrogen gas;

forming a dielectric layer lining at least the upper sidewalls of each trench;

during the time between the annealing and forming the dielectric layer, maintaining the semiconductor substrate in an inert environment to prevent formation of native oxide along upper sidewalls of each trench prior to forming the dielectric layer; and

forming a gate electrode in an upper portion of each trench.

16. The method of claim 15 wherein the forming a dielectric layer comprises performing an oxidation process to form a gate oxide layer along upper sidewalls of each trench.

17. The method of claim 16 wherein the oxidation process results in formation of a dielectric layer over the shield electrode in each trench.

18. The method of claim 15 wherein the forming of a dielectric layer comprises performing a nitridation process to form a silicon nitride layer along upper sidewalls of each trench.

19. The method of claim 15 further comprising:

prior to forming the dielectric layer, forming an inter-electrode dielectric layer over the shield electrode, the inter-electrode dielectric layer serving to insulate the shield electrode and the gate electrode from one another.

20. The method of claim 15 further comprising:

forming an epitaxial layer of a first conductivity type over a drain contact region of the first conductivity type, the epitaxial layer having a higher resistivity than the drain contact region, wherein the trenches extend into and terminate within the epitaxial layer.

21. The method of claim 15 further comprising:

forming a well region of a second conductivity type in the semiconductor substrate;

forming source regions of the first conductivity type in the well region; and

forming heavy body regions of the second conductivity type in the well region.

22. The method of claim 15 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 700°

C. to 1200°

C. and at a pressure within a range of about 100 mTorr to 450 Torr.

23. The method of claim 15 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 960°

C. to 1160°

C. and at a pressure within a range of about 40 Torr to 240 Torr.

24. The method of claim 15 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 800°

C. to 1000°

C. and a pressure within the range of about 200 mTorr to 400 mTorr.

25. The method of claim 15 further comprising:

after forming the shield electrode;

annealing the semiconductor substrate in a first reactor in a hydrogen ambient under reduced pressure;

purging the first reactor to remove the hydrogen gas;

transferring the semiconductor substrate from the first reactor to a second reactor through a transport chamber having an inert ambient; and

forming the dielectric layer in the second reactor under atmospheric pressure.

26. The method of claim 15 further comprising:

after forming the shield electrode;

annealing the semiconductor substrate in a chamber having a hydrogen ambient under reduced pressure;

purging the chamber to remove the hydrogen gas;

filling the chamber with an inert gas; and

forming the dielectric layer in the chamber under atmospheric pressure.

27. A method of forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor substrate of a first conductivity type;

forming a shield dielectric layer lining lower sidewalls and bottom of each trench;

forming a shield electrode filling a bottom portion of each trench;

annealing the semiconductor substrate in an ambient including hydrogen gas;

performing an oxidation process to form a layer of gate oxide along upper sidewalls of each trench;

during the time between the annealing and performing an oxidation process, maintaining the semiconductor substrate in an inert environment to prevent formation of native oxide along upper sidewalls of each trench prior to forming the layer of gate oxide;

forming a gate electrode in an upper portion of each trench;

forming a well region of a second conductivity type in the semiconductor substrate;

forming source regions of the first conductivity type in the well region; and

forming heavy body regions of the second conductivity type in the well region.

28. The method of claim 27 wherein the oxidation process results in formation of a dielectric layer over the shield electrode in each trench.

29. The method of claim 27 further comprising:

prior to forming the dielectric layer, forming an inter-electrode dielectric layer over the shield electrode, the inter-electrode dielectric layer serving to insulate the shield electrode and the gate electrode from one another.

30. The method of claim 27 wherein the semiconductor substrate comprises an epitaxial layer over a drain contact region, the epitaxial layer having a higher resistivity than the drain contact region, wherein the well region is formed in the epitaxial layer, and the trenches extend through the well region and terminate within the epitaxial layer.

31. The method of claim 27 wherein the annealing of the semiconductor substrate is performed at a temperature within the range of about 700°

C. to 1200°

C. and at a pressure within a range of about 100 mTorr to 450 Torr.

32-40. -40. (canceled)