MEMORY DEVICE IN MOBILE PHONE

• US 20080201543A1
• Filed: 04/28/2008
• Published: 08/21/2008
• Est. Priority Date: 09/07/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Taeyoun
• Granted Patent: US 8,433,363 B2
• Time in Patent Office: Days
• US Class Current: 711/165
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

A memory device for a mobile phone is provided. The memory device includes a flash memory for storing program data and user data; an interface circuit for copying program data stored in the flash memory according to whether data stored in the flash memory is valid; a first Random Access Memory (RAM) for providing an operation area to store and execute the copied program data; and a second RAM for storing data generated during the execution of program data, wherein the first and second RAMs are independent memories.

Claims

1. A memory device for a mobile phone comprising:

a flash memory for storing program data and user data;

an interface circuit for copying program data stored in the flash memory according to whether data stored in the flash memory is valid;

a first Random Access Memory (RAM) for providing an operation area to store and execute copied program data; and

a second RAM for storing data generated while executing the copied program data,

wherein the first RAM and the second RAM are independent memories.

2. The memory device of claim 1, wherein the flash memory comprises a NAND-type flash memory.

3. The memory device of claim 1, wherein the interface circuit comprises an application-specific integrated circuit (ASIC) including a read-only memory (ROM) for storing program codes and an error correction circuit.

4. The memory device of claim 1, wherein the interface circuit comprises a first logic gate for generating a NAND CE (chip enable) signal for enabling the flash memory.

5. The memory device of claim 4, wherein the interface circuit further comprises a second logic gate for generating a CLE (command latch enable) signal for informing the flash memory that incoming data is a command.

6. The memory device of claim 5, wherein the interface circuit further comprises a third logic gate for generating a ALE (address latch enable) signal for informing the flash memory that the incoming data is an address.

7. The memory device of claim 6, wherein the third logic gate comprises:

an AND gate for receiving an address signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating the ALE signal.

8. The memory device of claim 5, wherein the second logic gate comprises:

an AND gate for receiving a command signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating the CLE signal.

9. The memory device of claim 4, wherein the first logic gate comprises:

an OR gate for receiving a CS (chip select) signal from the microprocessor and a CE (chip enable) signal from the microprocessor for generating the NAND CE signal.

10. A mobile communication device comprising:

an analog circuit for air interfacing the mobile communication device;

a user interface circuit for interfacing between the mobile communication device and a user;

a microprocessor (MPU) for providing overall control of the mobile communication device; and

a memory device including

a flash memory for storing program data and user data;

an interface circuit for interfacing the flash memory to the microprocessor, wherein the interface circuit is an application-specific integrated circuit (ASIC) including a read-only memory (ROM) for storing program codes and an error correction circuit;

a first memory for copying the program data of the flash memory; and

a second memory for executing the program data of the first memory,

wherein the first memory and the second memory are independent memories.

11. The mobile communication device of claim 10, wherein the flash memory comprises a NAND-type flash memory.

12. The mobile communication device of claim 10, wherein the first and second memories comprise random-access memories (RAM).

13. The mobile communication device of claim 10, wherein the interface circuit comprises a first logic gate for generating a NAND CE (chip enable) signal for enabling the flash memory.

14. The mobile communication device of claim 13, wherein the first logic gate comprises:

an OR gate for receiving a CS (chip select) signal from the microprocessor and a CE (chip enable) signal from the microprocessor for generating the NAND CE signal.

15. The mobile communication device of claim 13, wherein the interface circuit further comprises:

a second logic gate for generating a CLE (command latch enable) signal for informing the flash memory that incoming data is a command.

16. The mobile communication device of claim 15, wherein the interface circuit further comprises:

a third logic gate for generating a ALE (address latch enable) signal for informing the flash memory that the incoming data is an address.

17. The mobile communication device of claim 16, wherein the third logic gate comprises:

an AND gate for receiving an address signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating the ALE signal.

18. The mobile communication device as in claim 15, wherein the second logic gate comprises:

an AND gate for receiving a command signal from the microprocessor and a CS (chip select) signal from the microprocessor for generating the CLE signal.