WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES

• US 20080201597A1
• Filed: 08/22/2007
• Published: 08/21/2008
• Est. Priority Date: 08/24/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chong, Yan, Sung, Chiakang, Huang, Joseph, Wang, Bonnie I., Chu, Michael H.M.
• Granted Patent: US 8,122,275 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Claims

1. A memory interface comprising:

a first pin to output a first signal;

a first delay circuit to receive a first clock signal and to output a plurality of phase-shifted versions of the first clock signal; and

a first output circuit coupled to the first pin and coupled to receive the plurality of phase-shifted versions of the first clock signal, the first output circuit including a first multiplexer for selecting a first one of the plurality of phase-shifted versions of the first clock signal, wherein the first output circuit synchronizes the first signal with the selected first one of the first plurality of phase-shifted versions of the first clock signal

2. The memory interface of claim 1 further comprising:

a second pin to output a second signal; and

a second output circuit coupled to the second pin and coupled to receive the plurality of phase-shifted versions of the first clock signal, the second output signal including a second multiplexer for selecting a second one of the first plurality of phase-shifted versions of the first clock signal, wherein the second output circuit synchronizes the second signal with the selected second one of the first plurality of phase-shifted versions of the first clock signal.

3. The memory interface of claim 1, wherein the first delay circuit provides a maximum delay approximately equal to a period of the first clock signal.

4. The memory interface of claim 2, wherein the first multiplexer is responsive to a first multiplexer control signal and the second multiplexer is responsive to a second multiplexer control signal.

5. The memory interface of claim 4, wherein the first and second multiplexer control signals are determined from a calibration mode used to measure skew.

6. The memory interface of claim 1, wherein the first output circuit includes a first flip-flop clocked by the first clock signal and a second flip-flop clocked by the selected first one of the first plurality of phase-shifted versions of the first clock signal.

7. The memory interface of claim 6, wherein the first output circuit includes a third register synchronized with an inverse of the first clock signal and connected between the first and second registers, wherein the third register transfers the first signal between the first and second registers.

8. The memory interface of claim 2, wherein the first pin is to output a DQ signal and the second pin outputs a DQS signal.

9. A memory interface comprising:

a first delay line to receive a first clock signal and to output a plurality of phase-shifted versions of the first clock signal;

a first output circuit including a first set of output pins, wherein a first portion of the first set of output pins outputs first signals, wherein the first output circuit selects a first one of the plurality of phase-shifted versions of the first clock signal and synchronizes the first signals with one of the first plurality of phase-shifted versions of the first clock signal

10. The memory interface of claim 9 further comprising:

a second output circuit including a second set of output pins, wherein a second portion of the second set of output pins outputs second signals, wherein the second output circuit selects a second one of the first plurality of phase-shifted versions of the first clock signal and synchronizes the second signals with the second one of the first plurality of phase-shifted versions of the first clock signal.

11. The memory interface of claim 10, wherein the first one of the first plurality of phase-shifted versions of the first clock signal is the same as the second one of the first plurality of phase-shifted versions of the first clock signal.

12. The memory interface of claim 10, wherein the first one of the first plurality of phase-shifted versions of the first clock signal is the different from the second one of the first plurality of phase-shifted versions of the first clock signal.

13. The memory interface of claim 10, wherein the first portion of the first set of output pins includes at least one DQ pin and the second portion of the second set of output pins includes at least one DQS pin.

14. The memory interface of claim 9, wherein the first delay line provides a maximum delay approximately equal to a period of the first clock signal.

15. The memory interface of claim 9, wherein the first output circuit includes a first multiplexer connected with the first clock bus to select a first one of the plurality of phase-shifted versions of the first clock signal and the second output circuit includes a second multiplexer connected with the second clock bus to select a second one of the first plurality of phase-shifted versions of the first clock signal.

16. A method of providing signals comprising:

receiving a first clock signal;

generating a plurality of second clock signals by successively delaying the first clock signal;

selecting a first one of the plurality of second clock signals;

clocking a first output register with the selected first one of the second plurality of clock signals to provide a first signal; and

clocking a second output register to provide a second signal.

17. The method of claim 16 wherein the second output register is clocked by the first clock signal.

18. The method of claim 16 wherein the second output register is clocked by a clock signal that is the first clock signal delayed by a logic gate delay.

19. The method of claim 16 further comprising:

selecting a second one of the plurality of second clock signals; and

clocking a third output register with the second one of the plurality of second clock signals to provide a third signal.

20. The method of claim 19 wherein the first signal is a DQS signal, the second signal is a clock signal, and the third signal is a DQ signal.

21. The method of claim 16 wherein the delay between the third clock signal and the selected one of the second plurality of clock signals compensates for a delay in the second signal caused by a fly-by topology routing path.

22. The method of claim 16 wherein the first signal is a DQS signal and the second signal is a clock signal.