WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
First Claim
1. A memory interface comprising:
- a first pin to output a first signal;
a first delay circuit to receive a first clock signal and to output a plurality of phase-shifted versions of the first clock signal; and
a first output circuit coupled to the first pin and coupled to receive the plurality of phase-shifted versions of the first clock signal, the first output circuit including a first multiplexer for selecting a first one of the plurality of phase-shifted versions of the first clock signal, wherein the first output circuit synchronizes the first signal with the selected first one of the first plurality of phase-shifted versions of the first clock signal
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Accused Products
Abstract
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
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Citations
22 Claims
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1. A memory interface comprising:
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a first pin to output a first signal; a first delay circuit to receive a first clock signal and to output a plurality of phase-shifted versions of the first clock signal; and a first output circuit coupled to the first pin and coupled to receive the plurality of phase-shifted versions of the first clock signal, the first output circuit including a first multiplexer for selecting a first one of the plurality of phase-shifted versions of the first clock signal, wherein the first output circuit synchronizes the first signal with the selected first one of the first plurality of phase-shifted versions of the first clock signal - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory interface comprising:
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a first delay line to receive a first clock signal and to output a plurality of phase-shifted versions of the first clock signal; a first output circuit including a first set of output pins, wherein a first portion of the first set of output pins outputs first signals, wherein the first output circuit selects a first one of the plurality of phase-shifted versions of the first clock signal and synchronizes the first signals with one of the first plurality of phase-shifted versions of the first clock signal - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of providing signals comprising:
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receiving a first clock signal; generating a plurality of second clock signals by successively delaying the first clock signal; selecting a first one of the plurality of second clock signals; clocking a first output register with the selected first one of the second plurality of clock signals to provide a first signal; and clocking a second output register to provide a second signal. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification