Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof

• US 20080201622A1
• Filed: 03/04/2008
• Published: 08/21/2008
• Est. Priority Date: 01/06/2000
• Status: Active Grant

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Hiew, Siew Sin, Shen, Ming-Shiang, Lee, Charles C., Ma, Abraham Chih-Kang, Yu, I-Kang
• Granted Patent: US 7,802,155 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.

Claims

1. A method of testing a plurality of non-volatile memory (NVM) modules comprising:

conducting an initial open/short test on each of the plurality of NVM modules;

dividing the plurality of NVM modules into first and second groups, the first group contains said each of the plurality of NVM modules fails in the initial open/short test, while the second group contains said each of the plurality of NVM modules passes the initial open/short test;

conducting a temperature and voltage test on each of the second group of the NVM modules;

dividing the second group into third and fourth groups, the third group contains said each of the second group that fails the temperature and voltage test and the fourth group contains said each of the second group that passes the temperature and voltage test;

conducting a function test on each of the fourth group of the NVM modules;

dividing the fourth group into fifth and sixth groups, the fifth group includes said each of the fourth group that fails the function test and the sixth group includes said each of the fourth group that passes the function test; and

sending all of the first, third and fifth group of the NVM modules to a rework unit for fixing failure-causing defect;

wherein the open/short test is configured to detect any open and/or short condition, wherein the temperature and voltage test is configured to determine whether operating temperature and voltage tolerance are met, and wherein the function test is configured to verify whether data stored in NVM cells are reliable.

2. The method of claim 1 further comprising:

conducting an industrial grade test on each of the sixth group of the NVMs; and

dividing the sixth group into an industrial grade group and a commercial grade group of the NVMs, wherein the industrial grade test is configured to ensure operating temperature between −

40 and 85 degree Celsius.

3. The method of claim 1, said conducting the function test further comprising:

coupling at least one of the sixth group of the NVM modules to a plurality of NVM test modules mounted on a main testing platform, each of the at least one of the sixth group of the NVM modules corresponds to a respective one of the plurality of NVM test modules;

initializing each of the at least one of the sixth group of the NVM modules by the main testing platform; and

verifying data written to said each the at least one of the sixth group with a test vector created by the respective one of the NVM test modules.

4. The method of claim 3, initializing said each of the at least one of the sixth group of the NVM modules further comprising:

receiving a command from the host at said each of the at least one of the sixth group of the NVM modules to check manufacturer'"'"'s identification (ID) of NVM;

sending the ID to the main testing platform to obtain a set of specific characteristics corresponding to the ID in a database stored thereon;

receiving a boot code and a run code to perform a self test; and

when the self test passes, formatting said each of the at least one of the sixth group of the NVM modules and loading an operating system image thereto.

5. The method of claim 4, wherein the ID is read using a predetermined slow timing in all channels and all NVM chip selections.

6. The method of claim 4, wherein the specific characteristics include NVM timing parameters, clock rates, number of address cycles, total capacity.

7. The method of claim 6, receiving the boot code and the run code comprises receiving the NVM timing parameters at NVM interface in said each of the at least one of the sixth group of the NVM modules.

8. The method of claim 7, wherein the run code is customized by the host with the specific characteristics corresponding to the ID of said each of the at least one of the sixth group of the NVM modules.

9. The method of claim 4, further comprises determining a bad block list to ensure number of bad blocks is within an acceptable threshold for said each of the at least one of the sixth group of the NVM modules.

10. The method of claim 3, wherein the test vector comprises a known sequence of data bits.

11. The method of claim 3, wherein the test vector comprises a repeatable random sequence of data bits that is produced by a pseudo random number generator.

12. The method of claim 3, wherein the test vector is written to a portion of NVM in a predefined direction according to a special function test command.

13. The method of claim 12, the predefined direction includes forward and backward.

14. An apparatus for testing a plurality of non-volatile memory (NVM) modules comprising:

a main testing platform with a central processing unit mounted thereon;

a plurality of NVM test modules coupling to the main testing platform, each of the test modules is configured to receive respective one of the plurality of NVM modules to be tested and each of the plurality of NVM test modules comprises;

an input/output (I/O) interface configured to transmit commands and data between the main testing platform and said each of the plurality of the NVM test modules;

a data generator configured for generating a repeatable sequence of data for a test vector to be written to the respective one of the plurality of NVM modules under test;

an address generator configured for creating start and end addresses for the test vector;

a comparator configured to compare the repeatable sequence of data of the test vector and data retrieved from the respective one of the NVM modules after the test vector has been written into;

a memory space configured to store comparison status; and

a set of indicators configured to show test result.

15. The apparatus of claim 14, wherein the data generator comprises a pseudo random number generator (RNG) and a seed register.

16. The apparatus of claim 15, wherein each the received commands determines value in the seed register.

17. The apparatus of claim 14, wherein the start and end addresses are generated such that a portion of NVM of the respective one of the NVM modules can be tested.

18. A system for testing a plurality of non-volatile memory (NVM) modules comprising:

a computer;

a NVM tester coupling to the computer via an external bus, the NVM tester comprises a plurality of slots, each of the slots is configured to receive respective one of the plurality of NVM modules to be tested;

the NVM tester further comprises;

an external bus interface configured to transmit data, control signals and power between the NVM tester and the computer;

a data generator configured for generating a repeatable sequence of data for a test vector to be written to the plurality of NVM modules under test;

an address generator configured for creating start and end addresses for the test vector;

a comparator configured to compare the repeatable sequence of data of the test vector and data retrieved from the NVM modules after the test vector have been written into;

a memory space configured to store comparison status; and

a set of indicators configured to show test result.

19. The system of claim 18, further comprises a NVM module detector integrated on the NVM tester, the detector comprises detection logic and resource allocation logic.

20. The system of claim 18, wherein the external bus is a Universal Serial Bus.