SEMICONDUCTOR STRUCTURES AND MEMORY DEVICE CONSTRUCTIONS

• US 20080203453A1
• Filed: 05/07/2008
• Published: 08/28/2008
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 7,915,692 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Claims

1-53. -53. (canceled)

54. A semiconductor structure, comprising:

a semiconductor substrate;

a nitride-containing material lattice over the substrate; and

an array of non-nitride regions spaced from one another by segments of the lattice, wherein the nitride-containing material lattice surrounds the non-nitride regions in two orthogonal dimensions;

the array having a defined first pitch along a first axis and a defined second pitch along a second axis substantially orthogonal to the first axis;

the second pitch being about twice as big as the first pitch.

55. The structure of claim 54 wherein the nitride-containing material comprises silicon nitride.

58. The structure of claim 54 wherein the non-nitride regions comprise silicon dioxide.

103. The structure of claim 54, wherein the non-nitride regions are pillars that are elevationally separated from the nitride-containing lattice.

104. The structure of claim 54, wherein a first non-nitride region further comprises a source region formed at a top portion of a first pillar, and wherein a second non-nitride region further comprises a drain region formed at a top portion of a second pillar.

105. The structure of claim 104, further comprising a channel connecting the source region to the drain region, wherein a portion of the channel is formed in a connecting portion of semiconductor material that connects the first and second pillars.

106. The structure of claim 104, wherein the first pillar and the second pillar comprise conductively-doped epitaxial silicon.

56. (canceled)

57. (canceled)

59. (canceled)

60. (canceled)

61. A semiconductor structure, comprising:

a semiconductor substrate;

a gateline over the substrate; and

an array of non-gateline regions spaced from one another by segments of the gateline;

the array having a defined first pitch along a first axis and a defined second pitch along a second axis substantially orthogonal to the first axis;

the second pitch being about twice as big as the first pitch;

the non-gateline regions comprising elevationally-elongated source/drain regions forming source/drain pairs, wherein the source/drain pairs comprise one source region adjacent along the first axis to one drain region;

the gateline and source/drain pairs together forming a plurality of transistor constructions in which the source and drain regions of the source/drain pairs are gatedly connected to one other through the gateline, wherein the gateline comprises horizontally elongated segments on opposite sides of the source/drain pairs, the gateline being formed parallel to the first axis.

62. The structure of claim 61 wherein the gateline comprises at least one metal.

64. The structure of claim 61 wherein the gateline comprises conductively-doped silicon.

67. The structure of claim 61 wherein at least some of the elevationally-elongated source/drain regions comprise conductively-doped epitaxial silicon.

70. The structure of claim 61 wherein at least some of the elevationally-elongated source/drain regions comprise conductively-doped polycrystalline silicon.

73. The structure of claim 61 wherein some of the elevationally-elongated source/drain regions consist essentially of conductively-doped epitaxial silicon and others consist essentially of conductively-doped polycrystalline silicon.

74. The structure of claim 73 wherein source/drain regions consisting essentially of conductively-doped epitaxial silicon are gatedly connected to source/drain regions consisting essentially of conductively-doped polycrystalline silicon.

75. The structure of claim 61 wherein the non-gateline regions comprise dielectric material separating the elevationally-elongated source/drain regions from the gateline.

107. The structure of claim 61, wherein the elevationally-elongated source/drain regions extend vertically above the gateline.

108. The structure of claim 107, further comprising a memory storage device connected to the drain region.

109. The structure of claim 108, wherein the memory storage device comprises a capacitor.

110. The structure of claim 107, further comprising a digit line connected to the source region.

111. The structure of claim 110, further comprising a processor in communication with the digit line.

112. The structure of claim 61, further comprising a channel connecting a selected source/drain pair, the channel comprising a connecting portion of semiconductor material positioned adjacent to the gateline, wherein the channel and the source/drain pairs form U-shaped transistors.

113. The structure of claim 112, further comprising a dielectric material positioned between the channel and the gateline.

114. The structure of claim 61, wherein the gateline is also formed in between the source and the drain of one source/drain pair.

115. The structure of claim 61, wherein the gateline is also formed in between source/drain pairs that are aligned along the first axis.

63. (canceled)

65. (canceled)

66. (canceled)

68. (canceled)

69. (canceled)

71. (canceled)

72. (canceled)

76-102. -102. (canceled)