FAST SWITCHING POWER INSULATED GATE SEMICONDUCTOR DEVICE

• US 20080203457A1
• Filed: 01/28/2008
• Published: 08/28/2008
• Est. Priority Date: 01/21/2003
• Status: Active Grant

• Current Assignee: Ambixtra (Pty) Ltd.
• Original Assignee: Northwest University
• Inventors: De Jager, Ocker Cornelis, Visser, Barend
• Granted Patent: US 8,063,426 B2
• Time in Patent Office: Days
• US Class Current: 257/312
• CPC Class Codes: H01L 25/07 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches

Abstract

An insulated gate semiconductor device (30) includes a gate (34), a source terminal (36), a drain terminal (38) and a variable input capacitance at the gate. A ratio between the input capacitance (C_fiss) when the device is on and the input capacitance C_iiss when the device is off is less than two and preferably substantially equal to one. This is achieved in one embodiment of the invention by an insulation layer 32 at the gate having an effective thickness d_ins larger than a minimum thickness.

Claims

1. An insulated gate device comprising a gate connected to a gate terminal and having a variable input capacitance means adjacent to the gate terminal, said means comprising a variable capacitance such that as the device is switched between an off state and an on state, a ratio (C_fiss/C_iiss) between a final value of the capacitance (C_fiss) when the device is on and an initial value of the capacitance (C_iiss) when the device is off is 1<

C_fiss/C_iiss<

2.0.

2. A device as claimed in claim 1 comprising a power metal oxide silicon field effect transistor (MOSFET).

3. A device as claimed in claim 1 wherein said variable input capacitance means provides a capacitance such that the ratio (C_fiss/C_iiss) is 1<

C_fiss/C_iiss<

1.5.

4. A device as claimed in claim 3 wherein said variable input capacitance means provides a capacitance such that the ratio is 1<

C_fiss/C_iiss<

1.2.

5. A device as claimed in claim 1, wherein said variable input capacitance means comprises a capacitor between the gate terminal and the gate of the device.

6. A device as claimed in claim 2 wherein the MOSFET has a vertical structure in that the gate and a source of the device are provided on one face of a chip body of the device and a drain of the MOSFET is provided on an opposite face of the body, wherein said variable input capacitance means comprises a capacitor between the gate terminal and the gate of the device.

7. A device as claimed in claim 6 wherein the capacitor is integrated on the chip body.

8. A device as claimed in claim 7 wherein the capacitor is superimposed on the gate of the MOSFET.

9. A device as claimed in claim 5 wherein the capacitor is a discrete component connected in series between the gate and the gate terminal and packaged in the same package.

10. A device as claimed in claim 5 wherein the gate is connected directly to a fourth terminal of the device.

11. A device as claimed in claim 9 wherein biasing resistors connected to the gate are included in the same package.

12. A device as claimed in claim 1 wherein said variable input capacitance means comprises an insulation layer at the gate of the device.

13. A device as claimed in claim 1 wherein said variable capacitance means is comprised in said gate.

14. An insulated gate device comprising a gate, the device having a capacitance at the gate, where a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio between a final value of the capacitance when the device is on and an initial value of the capacitance when the device is off is smaller or equal to a second ratio of a maximum charge receivable on the gate and a charge required to reach a threshold voltage of the gate of the device.

15. An insulated gate device comprising a gate, the device having a capacitance at the gate, where a value of the capacitance is a function of an effective thickness of an insulation layer at the gate, the effective thickness of the insulation layer being selected to ensure that a first ratio between a final value of the capacitance when the device is on and an initial value of the capacitance when the device is off is smaller or equal to a second ratio of a maximum voltage applyable to the gate and a threshold voltage required on the gate to switch the device on.

16. An insulated gate device comprising a gate and an insulation layer at the gate, the layer having an effective thickness (d) of at least a quotient of a device parameter and a ratio of maximum charge accommodatable on the gate and a minimum charge required on the gate for complete switching, minus one (1), the device parameter being equal to the product of an effective gate capacitance area (A) and a difference between an inverse of a first value of a gate capacitance of the insulated gate device, that is when the device is off and an inverse of a second value of the gate capacitance, that is when the device is on.

17. A method of driving an insulated gate semiconductor device, the device comprising an insulation layer at a gate thereof providing a capacitance which varies between an initial value when the device is off and a final value when the device is on, the method comprising the step of depositing at least a Miller charge on the gate while the capacitance has said initial value.

18. A method as claimed in claim 18 comprising the step of depositing substantially sufficient charge for a desired steady state switched on state of the device on the gate while the capacitance has said initial value.