ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY AND ARRAY

• US 20080203464A1
• Filed: 10/31/2007
• Published: 08/28/2008
• Est. Priority Date: 07/01/2004
• Status: Abandoned Application

• Current Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Application Number:
  US11/932,481
• Publication Number:
  US 20080203464A1
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory device, array and method of arranging where the memory device includes a memory cell region including a plurality of memory cells. Each memory cell includes a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. Cell lines extend among the memory cells. A connection region is provided for electrically coupling contacts and one or more of the cell lines. A non-memory region has embedded logic. Memory cells are arrayed at a cell pitch, with cell lines extending from cell to cell and arrayed substantially at the cell pitch, and with contacts arrayed substantially at the cell pitch forming a high density memory device.

Claims

1. A memory device comprising,

a memory cell region including,

a plurality of memory cells, each memory cell including,

a source, a drain and a channel between the source and the drain,

a channel dielectric,

a charge storage region,

an electrically alterable conductor-material system in proximity to the charge storage region,

a plurality of cell lines extending among the memory cells,

a plurality of contacts.

a connection region for electrically coupling one or more of the contacts and one or more of the cell lines,

a non-memory region having embedded logic.

2. The memory device of claim 1 wherein,

the conductor-material system includes,

a first conductive region;

a dielectric region;

a second conductive region disposed adjacent to and insulated from the first conductive region by the dielectric region;

and wherein the charge storage region is a third region disposed adjacent to and insulated from the second conductive region.

3. The memory device of claim 1 wherein the contacts are selected from the group consisting of self-aligned contacts, borderless contacts and combinations thereof.

4. The memory device of claim 1 wherein one or more of the contacts are in contact holes arranged substantially in alignment with the cell lines, wherein the conductor-material system has one or more conductors, and wherein the contact holes include sidewall insulators to prevent the contacts from shorting to the conductors.

5. The memory device of claim 4 wherein the sidewall insulators are one or more materials selected from the group consisting of oxide, nitride, oxynitride and alloys thereof.

6. The memory device of claim 1 wherein the connection region includes a plurality of contact insulators where each of one or more of the contacts is located in proximity to a pair of the contact insulators.

7. The memory device of claim 6 wherein the contact insulators are one or more materials selected from the group consisting of oxide, nitride, oxynitride and alloys thereof.

8. The memory device of claim 1 wherein the plurality of cell lines includes first cell lines extending into the connection region, wherein one or more of the contacts are first contacts in the connection region and wherein one or more of the first contacts are electrically coupled to one or more of the first cell lines.

9. The memory device of claim 8 wherein the connection region further includes a plurality of contact insulators, each of the contact insulators aligned substantially between pairs of the first cell lines, and wherein each pair of the contact insulators has one or more of the first contacts arranged substantially there between.

10. The memory device of claim 1 wherein the non-memory region includes one or more of the contacts as non-memory region contacts and where one or more of the non-memory region contacts electrically couples to one or more of the cell lines.

11. The memory device of claim 1 wherein the plurality of cell lines includes one or more first cell lines extending into the non-memory region where one or more of the first cell lines electrically couples the embedded logic without an intermediary element or with a conductive intermediary element.

12. The memory device of claim 11 wherein the conductive intermediary element is selected from the group consisting of contacts, diffusions, metal lines and transistors or combinations thereof.

13. The memory device of claim 1 wherein the embedded logic includes one or more transistors, each transistor having transistor terminals and wherein at least one transistor terminal is electrically coupled to at least one of the cell lines.

14. The memory device of claim 1 wherein the connection region includes a first connection region and one or more of the contacts are first contacts in the first connection region and further including a second connection region wherein one or more of the contacts are second contacts in the second connection region wherein one or more of the plurality of cell lines includes first cell lines extending to the first connection region for electrically coupling to one or more of the first contacts and includes second cell lines extending to the second connection region for electrically coupling to one or more of the second contacts.

15. A memory device comprising,

a memory cell region including,

a plurality of memory cells arrayed at a cell pitch, each memory cell including,

a source, a drain and a channel between the source and the drain,

a channel dielectric,

a charge storage region,

an electrically alterable conductor-material system in proximity to the charge storage region,

a plurality of cell lines extending from cell to cell and arrayed substantially at the cell pitch,

a plurality of contacts arrayed substantially at the cell pitch, one or more of the contacts electrically coupling to one or more cell lines.

16. The memory device of claim 15 further including a connection region wherein first contacts of the plurality of contacts are in the connection region wherein the connection region includes a plurality of contact insulators, each of the contact insulators aligned substantially between pairs of the cell lines and wherein each pair of the contact insulators has one or more of the first contacts arranged substantially there between.

17. The memory device of claim 15 further including a non-memory region having embedded logic and wherein the plurality of cell lines includes one or more first cell lines extending into the non-memory region, the first cell lines electrically coupling the embedded logic without an intermediary element or with a conductive intermediary element.

18. The memory device of claim 17 wherein the conductive intermediary element is selected from the group consisting of contacts, diffusions, metal lines and transistors or combinations thereof.

19. The memory device of claim 17 wherein the embedded logic includes one or more transistors, each transistor having a first terminal, a second terminal and a gate terminal and wherein for one or more of the transistors, the first terminal electrically couples to a first non-memory region contact, the second terminal electrically couples to a second non-memory region contact and the gate electrically couples to a gate non-memory region contact.

20. The memory device of claim 19 wherein,

a first one of the transistors has a first-transistor first terminal electrically coupled to a first one of the first cell lines, has a first-transistor second terminal electrically coupled to a second one of the first cell lines whereby enabling a first-transistor gate electrically couples the first one of the first cell lines and the second one of the first cell lines.

21. The memory device of claim 19 wherein,

a first one of the transistors has a first-transistor first terminal connected to a first one of the first cell lines, has a first-transistor second terminal connected to a second one of the first cell lines whereby enabling a first-transistor gate electrically couples the first one of the first cell lines and the second one of the first cell lines,

a second one of the transistors has a second-transistor first terminal connected to the second one of the first cell lines, has a second-transistor second terminal connected to a third one of the first cell lines whereby enabling a second-transistor gate electrically couples the second one of the first cell lines and the third one of the first cell lines.

22. A method of arranging a memory device comprising,

in a memory region,

arranging a memory cell region including,

arranging a plurality of memory cells, including for each memory cell,

arranging a source, a drain and a channel between the source and the drain,

arranging a channel dielectric,

arranging a charge storage region,

arranging an electrically alterable conductor-material system in proximity to the charge storage region,

arranging a plurality of contacts.

arranging a connection region for electrically coupling one or more of the contacts and one or more of the cell lines,

arranging a non-memory region having embedded logic.

23. The method of claim 22 including arranging the plurality of contacts selected from the group consisting of arranging self-aligned contacts, arranging borderless contacts and combinations thereof.

24. A memory device comprising:

a non-memory region,

a memory region including,

a memory cell region having,

a plurality of memory cells, each memory cell including,

a source, a drain and a channel between the source and the drain,

a channel dielectric,

a charge storage region,

an electrically alterable conductor-material system in proximity to the charge storage region,

a connection region including a plurality of contacts, each contact electrically coupling to a cell line,

a plurality of cell lines extending among the memory cells in the memory region,

one or more isolations in the memory device.

25. A memory device of claim 24 wherein the plurality of cell lines include bit lines at a bit-line pitch and wherein isolation is included in the memory cell region occurring at an isolation pitch greater than the bit-line pitch.