FIELD EFFECT TRANSISTOR HAVING AN INTERLAYER DIELECTRIC MATERIAL HAVING INCREASED INTRINSIC STRESS

• US 20080203487A1
• Filed: 10/17/2007
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Finken, Michael, Richter, Ralf, Streck, Christof, Hohage, Joerg
• Application Number:
  US11/873,547
• Publication Number:
  US 20080203487A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current of the P-channel transistors may be increased by 2% and more while not unduly affecting the performance of the N-channel transistors.

Claims

1. A method, comprising:

forming a first etch stop layer above a P-channel transistor; and

forming an interlayer dielectric material above said first etch stop layer, said interlayer dielectric material comprising at least a layer portion having a compressive stress of approximately 400 MPa (Mega Pascal) or higher.

2. The method of claim 1, further comprising forming a contact opening in said interlayer dielectric material using said first etch stop layer as an etch stop.

3. The method of claim 1, wherein said interlayer dielectric material is comprised of silicon dioxide.

4. The method of claim 1, wherein said first etch stop layer has compressive stress.

5. The method of claim 3, wherein said interlayer dielectric material is formed by a plasma enhanced chemical vapor deposition process on the basis of one of TEOS and silane.

6. The method of claim 1, wherein said first etch stop layer comprises silicon and nitrogen.

7. The method of claim 6, wherein said first etch stop layer further comprises carbon.

8. The method of claim 1, further comprising forming a second etch stop layer above an N-channel transistor, said second etch stop layer having intrinsic tensile stress, wherein said interlayer dielectric material is formed above said first and second etch stop layers.

9. The method of claim 8, further comprising forming a dielectric buffer material above said second etch stop layer prior to forming said interlayer dielectric material above said first and second etch stop layers, said dielectric buffer material reducing a stress effect of said interlayer dielectric material on said N-channel transistor.

10. The method of claim 9, wherein said dielectric buffer material is formed so as to have tensile stress.

11. The method of claim 10, wherein said dielectric buffer material is formed on the basis of a thermal chemical vapor deposition process using TEOS.

12. A method, comprising:

forming a first etch stop layer above a first transistor;

forming a second etch stop layer above a second transistor, said first and second etch stop layers having at least one of a different amount and type of intrinsic stress; and

forming an interlayer dielectric material above said first and second etch stop layers, said interlayer dielectric material comprising a portion located above said first transistor and having an intrinsic stress level selected to adjust a strain level in a channel region of said first transistor.

13. The method of claim 12, wherein said intrinsic stress level is approximately 400 Mega Pascal or higher.

14. The method of claim 13, wherein said second etch stop layer is formed with an intrinsic tensile stress and said interlayer dielectric material is formed at least above said first transistor with compressive stress.

15. The method of claim 14, wherein forming said first and second etch stop layers comprises forming a dielectric material with intrinsic tensile stress above said first and second transistors and selectively reducing said tensile stress above said first transistor.

16. The method of claim 12, wherein forming said interlayer dielectric material comprises selectively forming a dielectric buffer layer above said second transistor, and forming a further dielectric layer having said intrinsic stress level above said dielectric buffer layer, said dielectric buffer layer differing in at least one of type and amount of intrinsic stress from said further dielectric layer.

17. The method of claim 16, wherein selectively forming said dielectric buffer layer comprises forming said dielectric buffer layer above said first and second transistors and removing a portion of said dielectric buffer layer from above said first transistor.

18. The method of claim 17, wherein selectively forming said dielectric buffer layer comprises forming said dielectric buffer layer above said first and second transistors with tensile stress and modifying a portion of said dielectric buffer layer located above said first transistor so as to reduce said tensile stress.

19. The method of claim 12, wherein said interlayer dielectric material is formed on the basis of one of TEOS and silane.

20. A semiconductor device, comprising:

a first transistor;

a first etch stop layer formed above said first transistor; and

a first interlayer dielectric material formed on said first etch stop layer, said interlayer dielectric material having an intrinsic stress level above said first transistor of approximately 400 Mega Pascal or higher.

21. The semiconductor device of claim 20, further comprising a second transistor and a second etch stop layer formed above said second transistor, said second etch stop layer having an intrinsic stress other than an intrinsic stress of said first interlayer dielectric material, wherein said first interlayer dielectric material is formed above said second etch stop layer.

22. The semiconductor device of claim 21, further comprising a dielectric buffer layer formed on said second etch stop layer, said dielectric buffer layer differing from said first interlayer dielectric material in at least one of type and amount of intrinsic stress.