Component, Power Component, Apparatus, Method Of Manufacturing A Component, And Method Of Manufacturing A Power Semiconductor Component

• US 20080203550A1
• Filed: 03/13/2007
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mahler, Joachim, Ewe, Henrik
• Granted Patent: US 8,097,936 B2
• Time in Patent Office: Days
• US Class Current: 257/675
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/117 Stacked arrangements of devices
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered.

Claims

1. A component, comprising:

a device carrier;

a device applied to the device carrier;

a first conducting layer grown onto the device and onto the device carrier; and

an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered.

2. The component as claimed in claim 1, wherein the insulating material is applied to the first conducting layer such that a different portion of the first conducting layer is exposed.

3. The component as claimed in claim 2, wherein the exposed portion of the first conducting layer comprises a larger layer thickness than that portion of the first conducting layer which is covered by the insulating material.

4. The component as claimed in claim 2, wherein the exposed portion of the conducting layer comprises at least two partial layers which are grown superimposed on one another.

5. The component as claimed in claim 2, wherein the insulating material defines a package within which the device carrier, the device, and the first conductive layer are embedded such that the exposed portion of the first conducting layer is located within the package.

6. The component as claimed in claim 2, wherein the device carrier comprises at least one first device carrier lead and one second device carrier lead which are insulated from one another, and wherein the device comprises first and second device contacts insulated from one another, the first conducting layer electrically connecting the second device contact and the second device carrier lead.

7. The component as claimed in claim 6, wherein the device carrier is a conductive device carrier.

8. The component as claimed in claim 6, wherein an exposed portion of the conducting layer essentially fully covers the second device contact.

9. The component as claimed in claim 6, wherein the first device contact is located on a first surface of the device which faces the conductive device carrier, and is electrically connected to the first device carrier lead, and wherein the second device contact is located on a second surface of the device which is opposite the first surface.

10. The component as claimed in claim 6, comprising an insulating layer at least partially applied to the device carrier and the device, the first conducting layer being located on the insulating layer.

11. The component as claimed in claim 10, wherein the insulating layer comprises a first via and a second via, the first via connecting the second device contact and the first conducting layer, and the second via connecting the second device carrier lead and the first conducting layer.

12. The component as claimed in claim 6, wherein the device carrier comprises a third device carrier lead insulated from the first and the second device carrier leads;

and

the device comprises a third device contact electrically connected to the third device carrier lead via a second conducting layer.

13. The component as claimed in claim 12, wherein the second conducting layer is at least partially located on the insulating layer.

14. The component as claimed in claim 13, wherein the insulating layer comprises a third via and a fourth via, the third via connecting the third device contact and the second conducting layer, and the fourth via connecting the third device carrier lead and the second conducting layer.

15. The component as claimed in claim 12, wherein the device is a semiconductor device, and wherein, preferably, the first device contact is a drain contact, the second device contact is a source contact, and the third device contact is a gate contact.

16. The component as claimed in claim 12, wherein the device is a power diode.

21. An apparatus, comprising:

a first component as claimed in claim 1; and

a second component, comprising;

a conductive device carrier comprising a first device carrier lead and a second device carrier lead insulated from one another;

a device comprising a first device contact and a second device contact, the first device contact being located on a first surface of the device which is facing the conductive device carrier of the second component, and being electrically connected to the first device carrier lead of the device carrier of the second component, and the second device contact being located on a second surface, opposite the first surface, of the device of the second component;

a package, wherein the conductive device carrier of the second component, the first conducting layer of the second component, and the device of the second component are at least partially embedded;

the first and the second components being superimposed on one another.

22. The apparatus as claimed in claim 21, wherein the device of the first and second components is a semiconductor device, wherein a first conducting layer of the second component is embedded within the package of the second component such that a portion of the first conducting layer of the second component is exposed over the device of the second component, the first device carrier lead of the first component being located essentially over the second device contact of the second component, and being electrically connected thereto.

23. The apparatus as claimed in claim 22, wherein the second device carrier lead of the second component is electrically connected to the second device carrier lead of the first component by a via through the package of the second component.

24. The apparatus as claimed in claim 23, wherein the device carrier of the first component and the device carrier of the second component comprise a third device carrier lead, which are electrically connected to one another by a via through the package of the second component.

25. The apparatus as claimed in claim 24, wherein the device of the first component is a power semiconductor device, and the device of the second component is a logic semiconductor device, the first device carrier lead of the second component being located essentially over the second device contact of the first component.

26. The apparatus as claimed in claim 25, comprising a first conducting layer electrically connecting the second device contact and the second device carrier lead.

27. The apparatus as claimed in claim 25, wherein the first device carrier lead of the second component is electrically connected to the second device contact of the first component.

28. The apparatus as claimed in claim 25, wherein the device carrier of the first component comprises a third device carrier lead insulated from the first and second device carrier leads of the first component, the third device carrier lead of the first component being electrically connected to the second device carrier lead of the second component by a first via through the package of the first component.

29. The apparatus as claimed in claim 28, wherein the device carrier of the second component comprises a third device carrier lead insulated from the first and second device carrier leads of the second component, wherein the device of the first component comprises a third device contact, and the third device carrier lead of the second component being electrically connected to the third device contact of the device of the first component by a second via through the package.

17. A power component, comprising:

a lead frame comprising at least one first lead, at least one second lead, and at least one third lead insulated from one another;

a semiconductor power device comprising a first contact on a first surface of the semiconductor power device, comprising a second contact on a second surface, opposite the first surface, of the semiconductor power device, and comprising a control contact, the first contact of the semiconductor power device being electrically connected to the first lead of the lead frame;

an insulating layer which at least partially covers the lead frame and the semiconductor power device, the insulating layer comprising, at least in the areas of the second and third leads of the lead frame and in the area of the second contact and of the control contact of the semiconductor power device, first, second, third, and fourth openings exposing the second and third leads of the lead frame and the second contact and the control contact of the semiconductor power device;

a first conducting layer applied to the insulating layer and extending into the first and third openings in the insulating layer, and connecting the second lead of the lead frame to the second contact of the semiconductor power device; and

a second conducting layer applied to the insulating layer and extending into the second and fourth openings in the insulating layer, and connecting the third lead of the lead frame to the control contact of the semiconductor power device; and

a package, wherein the lead frame, the semiconductor power device, and the first conducting layer, and the second conducting layer are at least partially embedded such that a portion of the first conducting layer remains exposed over the semiconductor power device.

18. The power component as claimed in claim 17, wherein the first contact is a drain contact, the second contact is a source contact, and the control contact is a gate contact.

19. The power component as claimed in claim 17, wherein the semiconductor power device is a power IC.

20. An apparatus, comprising:

a first means for signal processing comprising a first contactor and a second contactor;

a second means for supporting the first means, the second means comprising two lead means insulated from one another, the first lead means being electrically connected to the first contact means, and the second lead apparatus being conductively connected to the second contact means via a third means; and

a fourth means for at least partially embedding the first, second, and third means such that at least a portion of the third means is exposed over the first means.

30. A method of manufacturing a component, comprising:

providing a device carrier;

providing a device;

applying the device to the device carrier;

growing a first conducting layer onto the device and onto the device carrier; and

applying an insulating material to the first conducting layer in such a manner that only a portion of the first conducting layer is covered.

31. The method as claimed in claim 30, wherein applying the insulating material to the first conducting layer is performed such that a different portion of the first conducting layer is exposed.

32. The method as claimed in claim 31, wherein the step of growing the first conducting layer is performed such that the exposed portion of the first conducting layer comprises a larger layer thickness than that portion of the first conducting layer which is covered by the insulating material.

33. The method as claimed in claim 31, wherein the step of growing the first conducting layer is performed such that the exposed portion of the conducting layer comprises at least two partial layers which are grown superimposed on one another.

34. The method as claimed in claim 31, wherein the step of applying the insulating material is performed such that the insulating material defines a package within which the device carrier, the device, and the first conductive layer are embedded such that the exposed portion of the first conducting layer is located within the package.

35. The method as claimed in claim 31, wherein the device carrier comprises at least one first device carrier lead and one second device carrier lead which are insulated from one another,

and wherein the step of applying the first conducting layer is performed such that the first conducting layer electrically connects the second device contact and the second device carrier lead.

36. The method as claimed in claim 31, wherein the device carrier is a conductive device carrier.

37. The method as claimed in claim 31, wherein the exposed portion is generated such that same essentially fully covers the second device contact.

38. The method as claimed in claim 31, the method further comprising:

generating an insulating layer between the first and the second device carrier leads of the device carrier, and on a portion of the second surface of the device, the step of generating the first conducting layer generating the first conducting layer on the insulating layer.

39. The method as claimed in claim 38, wherein the step of generating the insulating layer involves leaving at least one first opening for generating an electrical connection between the second device contact and the first conducting layer, and leaving at least one second opening for generating an electrical connection between the second device carrier lead and the first conducting layer;

or

wherein the method comprises an additional step of generating a first via through the insulating layer for electrically connecting the second device contact to the first conducting layer, and of generating a second via for connecting the second device carrier lead and the first conducting layer.

40. The method as claimed in claim 31, wherein the conductive device carrier comprises a third device carrier lead insulated from the first and the second device carrier leads;

the device comprises a third device contact located on the second surface of the device; and

the method comprises the following steps;

generating a second conducting layer electrically connecting the third device contact and the third device carrier lead.

41. The method as claimed in claim 40, wherein the step of generating the second conducting layer generates the second conducting layer on the insulating layer.

42. The method as claimed in claim 41, wherein the step of generating the insulating layer involves leaving at least one third opening for generating an electrical connection between the third device contact and the second conducting layer, and leaving at least one fourth opening for generating an electrical connection between the third device carrier lead and the second conducting layer;

or

wherein the method comprises an additional step of generating a third via through the insulating layer for electrically connecting the third device contact to the second conducting layer, and of generating a fourth via for connecting the third device carrier lead and the second conducting layer.

43. The method as claimed in claim 40, wherein the device is a power semiconductor device.

44. The method as claimed in claim 31, wherein the device is a power diode.

45. A method of manufacturing a power semiconductor component:

providing a conductive device carrier comprising a drain lead, a source lead, and a gate lead insulated from one another;

providing a power semiconductor device having a drain contact, a source contact, and a gate contact, the drain contact being located on a first surface of the power semiconductor device, and the source contact and the gate contact being located on a second surface opposite the first surface,

attaching the power semiconductor device such that the drain contact is located on and electrically connected to the drain lead;

applying the insulating layer;

structuring the insulating layer;

applying a seed layer by means of a deposition process;

lithographic structuring on the seed layer;

galvanic reinforcement of the seed layer after structuring;

removing the lithography layer;

second lithographic structuring on the galvanic deposition and/or other areas;

second galvanic reinforcement;

removing the seed layer between the planar connections by means of differential etching;

package encapsulation by enclosing the device carrier by molding compound in an injection molding process;

cleaning and tinning the package leads; and

labeling and separating the packages.