Through-Wafer Interconnection

• US 20080203556A1
• Filed: 05/18/2006
• Published: 08/28/2008
• Est. Priority Date: 05/18/2005
• Status: Active Grant

• Current Assignee: Kolo Medical, Ltd.
• Original Assignee: Kolo Technologies, Inc.
• Inventors: Huang, Yongli
• Granted Patent: US 8,105,941 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.

Claims

1. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising the steps of:

providing a conductive wafer having a front side and a backside;

forming a patterned trench in the conductive wafer by removing material of the conductive wafer, wherein the patterned trench has an annular circumferential opening generally dividing the conductive wafer along the opening into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor; and

adding a filler material into the patterned trench.

2. The method of claim 1, wherein the filler material is added into the patterned trench to function as a mechanical support between the inner portion and the outer portion.

3. The method of claim 1, wherein the filler material is a dielectric material for electrically insulate the inner portion from the outer portion.

4. The method of claim 1, wherein the patterned trench comprises a first trench portion having a first cross-sectional size and a second trench portion having a second cross-sectional size different from the first cross-sectional size.

5. The method of claim 1 wherein the through-wafer conductor has a first portion surrounded and defined by a first portion of the patterned trench and a second portion surrounded and defined by a second portion of the patterned trench, the second portion of the through-wafer conductor having a smaller cross-sectional size than the first portion of the through-wafer conductor.

6. The method of claim 1 wherein the conductive wafer has a top layer and a bottom layer which are two separate layers bonded together.

7. The method of claim 6 wherein the two separate layers of the conductive wafer are directly bonded together without an intervening layer of material.

8. The method of claim 1 wherein the conductive wafer is a doped silicon wafer.

9. The method of claim 1 wherein the conductive wafer is a doped silicon wafer having a top section and a bottom section which have different doping levels.

10. The method of claim 1 wherein the step of forming the patterned trench comprises the steps of:

forming a first portion of the patterned trench from one of the front side and the backside; and

forming a second portion of the patterned trench from the other side.

11. The method of claim 10 wherein the step of forming the patterned trench further comprises oxidizing the first portion of the patterned trench to form a stop layer on a bottom of the first portion to define a stop position, and wherein the step of forming the second portion of the patterned trench stops when the second portion of the patterned trench reaches the stop position.

12. The method of claim 10 wherein the step of forming the patterned trench further comprises adding a dielectric material in at least one of the first and the second portions of the patterned trench.

13. The method of claim 1, wherein at least a portion of the patterned trench is further fine-patterned within trench opening with open passages interlined with lines of unremoved conductive wafer material.

14. The method of claim 13 further comprising adding a filler material between the lines of unremoved conductive wafer material.

15. The method of claim 13 further comprising oxidizing the lines of unremoved conductive wafer material.

16. The method of claim 15 further comprising adding a filler material between the oxidized lines of unremoved conductive wafer material.

17. The method of claim 1 wherein the step of forming a patterned trench comprises forming a plurality of patterned trenches similarly characterized.

18. The method of claim 17 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches sharing a common trench side.

19. The method of claim 17 wherein the plurality of patterned trenches are arranged side-by-side in an array with neighboring patterned trenches separated by an intervening spacing.

20. The method of claim 19 wherein the intervening spacing is occupied by a conductive material for decoupling neighboring conductors.

21. The method of claim 20 wherein the conductive material in the intervening spacing comprises unremoved conductive material of the conductive wafer.

22. The method of claim 1 wherein the conductive wafer is a conductive silicon wafer, and the step of forming a patterned trench comprises:

forming a first portion of the patterned trench by etching from one of the front side and the backside of the conductive silicon wafer;

forming an oxide layer over surfaces of the first portion of the patterned trench;

removing at least part of the oxide layer on a bottom of the first portion of the patterned trench;

forming an enlarged cavity at the bottom of the first portion of the patterned trench by isotropic silicon etching;

forming a stop layer by oxidizing a bottom surface of the enlarged cavity; and

forming a second portion of the patterned trench by etching from the other side of the conductive silicon wafer to reach the stop layer.

23. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising the steps of:

providing a conductive wafer having a front side and a backside; and

forming a patterned trench in the conductive wafer by removing material of the conductive wafer,

wherein,

(a) the patterned trench has an annular circumferential opening generally dividing the conductive wafer along the opening into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor; and

(b) at least a portion of the patterned trench is further fine-patterned within trench opening with open passages interlined with lines of unremoved conductive wafer material.

24. The method of claim 23 wherein the lines of unremoved conductive wafer material form a framework between the inner portion and the outer portion of the conductive wafer to connect and support the two portions.

25. The method of claim 24 further comprising completely oxidizing at least part of the lines of unremoved conductive wafer material such that the framework is electrically insulative between the inner portion and the outer portion of the conductive wafer.

26. The method of claim 23 further comprising oxidizing the lines of unremoved conductive wafer material.

27. The method of claim 26 further comprising adding a filler material between the oxidized lines of unremoved conductive wafer material.

28. The method of claim 23 further comprising adding a filler material between the lines of unremoved conductive wafer material.

29. The method of claim 28 further comprising etching at least part of the lines of unremoved conductive wafer material.

30. The method of claim 29 further comprising adding another filler material within voids formed by removing the lines of unremoved wafer material.

31. The method of claim 23 further comprising the steps of:

adding a first dielectric material into a top portion of the patterned trench; and

adding a second dielectric material into a bottom portion of the patterned trench.

32. The method of claim 23 wherein the step of forming a patterned trench comprises the steps of:

forming an etch stop layer from a front side;

forming the patterned trench by etching from the backside to the etch stop layer.

33. The method of claim 23 wherein the step of forming a patterned trench comprises forming the patterned trench by deep silicon etching from the front side of the conductive wafer.

34. The method of claim 23 further comprising the steps of:

bonding a top conductive wafer onto the front side of the conductive wafer; and

forming a top patterned trench in the top conductive wafer by removing material of the top conductive wafer,

wherein,

(a) the top patterned trench has an annular circumferential opening generally dividing the top conductive wafer along the opening into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a top through-wafer conductor; and

(b) the top through-wafer conductor and the through-wafer conductor are conductively connected to form a combined through-wafer conductor.

35. The method of claim 34 wherein the top through-wafer conductor has a cross-sectional size significantly greater than that of the through-wafer conductor.

36. The method of claim 34 further comprising the step of:

before forming the top patterned trench, at least partially forming a device on or above the top conductive wafer.

37. A method for fabricating through-wafer interconnects in a microelectronic structure, the method comprising the steps of:

bonding a first conductive wafer and a second conductive wafer such that a bottom side of the first conductive wafer contacting a top side of the second conductive wafer;

forming a first portion of a patterned trench through a top side of the first conductive wafer; and

forming a second portion of the patterned trench through a backside of the second conductive wafer,

wherein the first portion and the second portion of the patterned trench each have an annular circumferential opening generally dividing the respective conductive wafer into an inner portion and an outer portion, the inner portion of the respective conductive wafer is insulated from the outer portion of the respective conductive wafer, and the inner portion of the first conductive wafer and the inner portion of the second conductive wafer are electrically connected to serves as a through-wafer conductor.

38. The method of claim 37 wherein the first conductive wafer and the second conductive wafer are directly bonded together without an intervening layer therebetween.

39. The method of claim 37 further comprising the steps of:

before bonding the first and the second conductive wafers, forming a cavity on the top side of the second conductive wafer, and oxidizing at least a bottom surface of the cavity to form an etch stop layer thereon, wherein the step of forming a bottom portion of the patterned trench comprises etching through the backside of the second conductive wafer to the etch stop layer.

40. The method of claim 37 further comprising the steps of:

after bonding the first and the second conductive wafers, fabricating at least a part of a microelectronic device on one of the first and the second conductive wafers.

41. The method of claim 37 wherein the second portion of the patterned trench has trench openings broader than that of the first portion of the patterned trench, whereby a second portion of the through-wafer conductor surrounded and defined by the second portion of the patterned trench has a smaller cross-sectional size than a first portion of the through-wafer conductor surrounded and defined by the second portion of the patterned trench.

42. The method of claim 37 wherein at least one of the first and the second conductive wafers is either pre-fabricated to contain at least part of a microelectronic device or allows fabricating a microelectronic device thereon after being bonded to the other conductive wafer.

43. The method of claim 37, wherein the second portion of the patterned trench is further fine-patterned within the trench openings with open passages interlined with lines of unremoved conductive wafer material.

44. The method of claim 43 wherein the lines of unremoved conductive wafer material form a framework between the inner portion and the outer portion of the conductive wafer to connect and support the two portions.

45. The method of claim 44 further comprising the step of:

completely oxidizing at least part of the lines of unremoved conductive wafer material such that the framework is electrically insulative between the inner portion and the outer portion of the conductive wafer.

46. A through-wafer interconnect which provides electrically conductive interconnection between electric contacts on a front side and a backside of a wafer in a microelectronic structure, the through-wafer interconnect comprising:

a through-wafer conductor passing through the front side of the wafer to the backside of the wafer;

an insulator surrounding at least a main body portion of the conductor; and

a frame surrounding the through-wafer conductor and the insulator, wherein at least a portion of the through-wafer conductor and a respective surrounding portion of the frame each comprise a native material of the wafer.

47. The through-wafer interconnect of claim 46 wherein the wafer is a conductive wafer.

48. The through-wafer interconnect of claim 46 wherein the through-wafer conductor comprises a top portion and a bottom portion which are different from each other in at least one aspect of cross-sectional size and material property.

49. The through-wafer interconnect of claim 46 wherein the insulator comprises a top portion and a bottom portion which are different from each other in at least one aspect of cross-sectional size and material property.

50. The through-wafer interconnect of claim 46 wherein the wafer comprises a top layer and a bottom layer bonded together.

51. The through-wafer interconnect of claim 46 wherein the insulator comprises a dielectric material added to an annular trench formed in the wafer by removing native material of the wafer.

52. The through-wafer interconnect of claim 46 wherein the insulator comprises lines of unremoved native material of the wafer patterned in an annular trench.

53. The through-wafer interconnect of claim 52 wherein the lines of unremoved native material of the wafer form a supporting framework between the conductor and the frame.

54. The through-wafer interconnect of claim 52 further comprising a filler material filled between the lines of unremoved native material of the wafer patterned in the annular trench.

55. The through-wafer interconnect of claim 52 wherein at least part the lines of unremoved native material is oxidized.

56. The through-wafer interconnect of claim 52 wherein at least part of the lines of unremoved native material of the wafer is completely oxidized.

57. The through-wafer interconnect of claim 46 wherein the insulator comprises a filler material filled in a trench.

58. The through-wafer interconnect of claim 46 wherein the frame comprises a zigzag shaped wall which is flexible through stretching or compressing.

59. A through-wafer interconnect component comprising:

a plurality of conductors arranged in an array, each conductor passing through a front side of a conductive wafer to a backside of a wafer;

an insulator surrounding each conductor; and

a frame supporting the plurality of conductors and the insulator, wherein at least a portion of each conductor and a portion of the frame each comprise a native material of the wafer.

60. The through-wafer interconnect of claim 59 wherein the insulator is disposed in a plurality of annular trenches each surrounding a respective conductor, the annular trenches being formed by removing a native material of the wafer.

61. The through-wafer interconnect of claim 59 wherein the frame has an outer peripheral wall and a plurality of inter-conductor walls, the outer peripheral wall defining a general area where the plurality of conductors and the insulator are disposed, and the plurality of inter-conductor walls dividing the general area into a plurality of sub-areas each containing one of the conductors and a respective portion of the insulator surrounding the conductor.

62. The through-wafer interconnect of claim 61 wherein the inter-conductor walls of the frame comprise a conductive material to function as a decoupling conductor between the plurality of conductors.

63. The through-wafer interconnect of claim 62 wherein the conductive material is the native material of the layer.

64. The through-wafer interconnect of claim 59 wherein the frame comprises a zigzag shaped wall which is flexible through stretching or compressing.