Boost buffer aid for reference buffer

• US 20080203977A1
• Filed: 11/09/2007
• Published: 08/28/2008
• Est. Priority Date: 11/10/2006
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Timothy J., Raimar, Nandakishore
• Granted Patent: US 8,564,252 B2
• Time in Patent Office: Days
• US Class Current: 320/166
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 17/962 Capacitive touch switches
• CPC Class Codes: H03K 2217/960725 Charge-transfer

Abstract

A circuit for charging a capacitive load to a reference voltage in a capacitive sensor measurement circuit includes a reference buffer, a boost buffer, and drive logic. The reference buffer and the boost buffer are coupled with the capacitive load to be charged. The boost buffer first charges the capacitive load towards the reference voltage at a first rate of charging, and then ceases charging. The reference buffer subsequently continues charging at a slower second rate to settle the voltage across the capacitive load to within a tolerable range of the reference voltage.

Claims

1. A method, comprising:

charging a capacitive load at a first rate of charging to cause a voltage level of the capacitive load to approach a reference voltage level;

terminating said charging the capacitive load at the first rate of charging; and

charging the capacitive load at a second rate of charging to cause the voltage level of the capacitive load to approach the reference voltage level, wherein the first rate of charging is faster than the second rate of charging.

2. The method according to claim 1, wherein said charging the capacitive load at the first rate of charging comprises operating a boost buffer connected with the capacitive load to drive current into the capacitive load.

3. The method according to claim 2, wherein terminating said charging the capacitive load at the first rate of charging comprises tristating the boost buffer in response to receiving an indication that the voltage level of the capacitive load has reached a threshold voltage level.

4. The method according to claim 1, further comprising monitoring the voltage level of the capacitive load concurrently with said charging the capacitive load at the first rate of charging.

5. The method according to claim 4, further comprising beginning said monitoring the voltage level of the capacitive load in response to receiving an indication that a current is being driven into the capacitive load.

6. The method according to claim 1, wherein said charging the capacitive load at the second rate of charging comprises operating a reference buffer connected with the capacitive load to settle the voltage level of the capacitive load towards the reference voltage.

7. The method according to claim 6, further comprising tristating the reference buffer in response to receiving an indication that a time period has elapsed.

8. The method according to claim 1, further comprising:

driving a first current into the capacitive load and a switching capacitive sensor;

terminating said driving the first current in response to receiving an indication that a settling time has elapsed;

driving a second current into the capacitive load until the voltage level of the capacitive load reaches a final voltage level; and

recording a number of counts detected during said driving the second current.

9. An apparatus for charging a capacitive load, comprising:

a current driver configured to charge the capacitive load at a first rate of charging to cause a voltage across the capacitive load to approach a reference voltage;

a drive logic module coupled with the current driver, wherein the drive logic module is configured to control an output state of the current driver; and

a reference buffer coupled with the capacitive load, wherein the reference buffer is configured to charge the capacitive load at a second rate of charging to cause the voltage across the capacitive load to approach the reference voltage, wherein the first rate of charging is faster than the second rate of charging.

10. The apparatus according to claim 9, further comprising a comparator module coupled with the drive logic module, wherein the comparator module is configured to monitor the voltage across the capacitive load.

11. The apparatus according to claim 10, wherein the comparator module is configured to begin monitoring the voltage across the capacitive load in response to an indication that a current is being driven into the capacitive load.

12. The apparatus according to claim 10, wherein the drive logic module is further configured to disable the current driver in response to receiving an indication from the comparator module that the voltage across the capacitive load has reached a threshold voltage level.

13. The apparatus according to claim 9, wherein the drive logic module is configured to disable the current driver by tristating an output of the current driver.

14. The apparatus according to claim 9, further comprising a reference buffer control module configured to control an output state of the reference buffer.

15. The apparatus according to claim 14, wherein the reference buffer control module is configured to disable the reference buffer in response to receiving an indication that a time period has elapsed.

16. The apparatus according to claim 9, wherein the capacitive load comprises an modulation capacitor coupled with the current driver.

17. The apparatus according to claim 9, further comprising a capacitive sensor coupled with the capacitive load and the current driver.

18. The apparatus according to claim 17, further comprising a comparator module coupled with the drive logic module, wherein the drive logic module is further configured to disable the current driver in response to receiving an indication from the comparator module that the voltage across the capacitive load has reached a threshold voltage level.

19. A device, comprising:

means for charging a capacitive load using a reference buffer; and

means for reducing a charge cycle duration associated with the means for charging the capacitive load.

20. The device according to claim 19, wherein said means for reducing the charge cycle duration comprises a boost buffer.