Video buffer management

• US 20080204604A1
• Filed: 02/26/2007
• Published: 08/28/2008
• Est. Priority Date: 02/26/2007
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Co. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Co. (HP Inc.)
• Inventors: Campbell, Robert
• Granted Patent: US 8,049,821 B2
• Time in Patent Office: Days
• US Class Current: 348/731
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/4331 Caching operations, e.g. of an advertisement for later insertion during playback
• CPC Class Codes: H04N 21/4334 Recording operations recording of a television signal H04N5/76; arrangements for recording or accumulating broadcast information or broadcast-related information H04H60/27
• CPC Class Codes: H04N 21/4383 Accessing a communication channel

Abstract

In one embodiment a video system comprises a first tuner, a first memory buffer coupled to the first tuner to receive a first video signal from the first tuner, a second tuner, a second memory buffer coupled to the second tuner to receive a second video signal from the second tuner, and a controller comprising logic to direct the first video signal from the first memory buffer to an output port, receive a signal to switch the output port from the first memory buffer to the second memory buffer, and in response to the signal, couple the output port to the second memory buffer without disrupting the operations of the first memory buffer.

Claims

1. A method to manage video buffer content in a multi-tuner video system, comprising:

storing a first video signal from a first tuner in a first memory buffer;

directing the first video signal to an output port;

storing a second video signal from a second tuner in a second memory buffer;

receiving a signal to switch the output port from the first memory buffer to the second memory buffer; and

in response to the signal, coupling the output port to the second memory buffer without disrupting the operations of the first memory buffer.

2. The method of claim 1, wherein storing a first video signal from a first tuner in a first memory buffer comprises:

receiving a first video signal in the first tuner; and

decoding the first video signal.

3. The method of claim 1, wherein storing a second video signal from a first tuner in a second memory buffer comprises:

receiving a second video signal in the second tuner; and

decoding the second video signal.

4. The method of claim 1, further comprising storing at least one of the first video signal or the second video signal in a file store.

5. The method of claim 1, further comprising:

receiving a signal to replay a portion of the video signal content stored in of the first memory buffer; and

in response to the signal, coupling a display input to the first memory buffer without disrupting the operations of the second memory buffer.

6. The method of claim 1, further comprising:

storing at least one of the first video signal or the second video signal in a file store.

7. A video system, comprising:

a first tuner;

a first memory buffer coupled to the first tuner to receive a first video signal from the first tuner;

a second tuner;

a second memory buffer coupled to the second tuner to receive a second video signal from the second tuner;

a controller comprising logic to;

direct the first video signal from the first memory buffer to an output port;

receive a signal to switch the output port from the first memory buffer to the second memory buffer; and

in response to the signal, couple the output port to the second memory buffer without disrupting the operations of the first memory buffer.

8. The video system of claim 7, further comprising logic to:

receive a first video signal in the first tuner; and

decode the first video signal.

9. The video system of claim 7, further comprising logic to:

receive a second video signal in the second tuner; and

decode the second video signal.

10. The video system of claim 7, further comprising logic to store at least one of the first video signal or the second video signal in a file store.

11. The video system of claim 7, further comprising logic to:

receive a signal to replay a portion of the video signal content stored in the first memory buffer; and

in response to the signal, couple the output port to the first memory buffer without disrupting the operations of the second memory buffer.

12. The video system of claim 7, further, further comprising:

a file store; and

logic to store at least one of the first video signal or the second video signal in the file store.

13. The video system of claim 7, further, further comprising a display coupled to the output port.

14. A computer program product comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to:

store a first video signal from a first tuner in a first memory buffer;

direct the first video signal to an output port;

store a second video signal from a second tuner in a second memory buffer;

receive a signal to switch the output port from the first memory buffer to the second memory buffer; and

in response to the signal, couple the output port to the second memory buffer without disrupting the operations of the first memory buffer.

15. The computer program product of claim 14, further comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to:

receive a first video signal in the first tuner; and

decode the first video signal.

16. The computer program product of claim 14, further comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to:

receive a second video signal in the second tuner; and

decode the second video signal.

17. The computer program product of claim 14, further comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to store at least one of the first video signal or the second video signal in a file store.

18. The computer program product of claim 14, further comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to:

receive a signal to replay a portion of the video signal content stored in of the first memory buffer; and

in response to the signal, couple a display input to the first memory buffer without disrupting the operations of the second memory buffer.

19. The computer program product of claim 14, further comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to store at least one of the first video signal or the second video signal in a file store.