ARC FAULT CIRCUIT INTERRUPTER AND METHOD OF PARALLEL ARC FAULT DETECTION

• US 20080204955A1
• Filed: 02/27/2007
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Elms, Robert T., PARKER, KEVIN L.
• Granted Patent: US 7,633,728 B2
• Time in Patent Office: Days
• US Class Current: 361/87
• CPC Class Codes: H02H 1/0015 Using arc detectors
• CPC Class Codes: H02H 1/043 to inrush currents H02H1/046 takes precedence; differential protection of transformers H02H7/045

Abstract

An arc fault circuit interrupter includes separable contacts, an operating mechanism, a current sensor sensing current flowing through the contacts and outputting a sensed current, and a processor determining and storing peak values of the sensed current for plural half-cycles. The processor provides arc fault detection, determines whether a first predetermined plurality of half-cycles occur in succession and correspond to non-unity power factor, and responsively inhibits the detection for a first predetermined time, and whether a second predetermined plurality of half-cycles occur in succession, each with smaller peak amplitude than that of an immediately preceding half-cycle of like or differing polarity, and responsively inhibits the detection for a second predetermined time. The processor determines that the detection is not inhibited for the first and second predetermined times, and responsively indicates that any of the half-cycles having a peak amplitude greater than a predetermined amount is a parallel arc.

Claims

1. An arc fault circuit interrupter comprising:

separable contacts;

a neutral conductor;

an operating mechanism structured to open and close said separable contacts;

a current sensor structured to sense current flowing through said separable contacts and output a sensed current value; and

a processor cooperating with said current sensor to determine and store a plurality of peak values of the sensed current value for a plurality of half-cycles of said current flowing through said separable contacts,

wherein said processor is structured to provide arc fault detection and to determine at least one of;

(a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor, and to responsively inhibit said arc fault detection for a first predetermined time, and

(b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity, and to responsively inhibit said arc fault detection for a second predetermined time, and

wherein said processor is further structured to determine that said arc fault detection is not inhibited for at least one of said first predetermined time and said second predetermined time, and to responsively indicate that at least one of said half-cycles of said current having a peak amplitude greater than or equal to a predetermined amount is a parallel arc.

2. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to indicate a parallel arc fault in response to a predetermined plurality of occurrences of said parallel arc, said occurrences each being separated from one another by no more than a third predetermined time.

3. The arc fault circuit interrupter of claim 2 wherein said processor is further structured to trip open said separable contacts in response to said indicate a parallel arc fault.

4. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to determine both of said (a) whether a first predetermined plurality of said half-cycles of said current occur in succession and correspond to a non-unity power factor and said (b) whether a second predetermined plurality of said half-cycles of said current occur in succession and each of said second predetermined plurality of said half-cycles of said current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of said current of like polarity or of differing polarity;

and wherein said processor is further structured to determine that said arc fault detection is not inhibited for both of said first predetermined time and said second predetermined time.

5. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to store said sensed current value over said plurality of half-cycles of said current flowing in said power circuit, and to ignore any of said half-cycles of said current having a peak amplitude less than said predetermined amount.

6. The arc fault circuit interrupter of claim 1 wherein said processor comprises at least one timer responsive to at least one of said inhibit said arc fault detection for a first predetermined time and said inhibit said arc fault detection for a second predetermined time.

7. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to sense a zero crossing of a line-to-neutral voltage between one of said separable contacts and said neutral conductor, and to determine whether said sensed current value corresponds to a non-unity power factor for each of said half-cycles of said current.

8. The arc fault circuit interrupter of claim 1 wherein said predetermined amount is equal to about 50 A peak.

9. The arc fault circuit interrupter of claim 1 wherein said peak values include a first peak value of the current one of said half-cycles and a second peak value of the previous one of said half-cycles having the same polarity as the current one of said half-cycles;

and wherein said processor is further structured to determine if said second peak value is greater than said first peak value plus a predetermined value.

10. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to determine if said peak values have exceeded said predetermined amount for each of the last about four of said half-cycles, and to determine a non-unity power factor for each of said last about four of said half-cycles.

11. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to determine if said peak values have exceeded said predetermined amount for each of the last about five to about seven of said half-cycles, and to determine if said peak values have declined for each of the last at least three of said half-cycles.

12. A method of detecting parallel arc faults in a power circuit, said method comprising:

(a) sensing a plurality of half-cycles of current flowing in said power circuit;

(b) providing arc fault detection of said current flowing in said power circuit;

(c) ignoring any of said half-cycles of current having a peak amplitude less than a predetermined amount;

(d) determining at least one of;

(i) whether a first predetermined plurality of said half-cycles of current occur in succession and have non-unity power factor and responsively inhibiting said arc fault detection for a first predetermined time, and

(ii) whether a second predetermined plurality of said half-cycles of current occur in succession and each of said second predetermined plurality of said half-cycles of current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of current of like polarity or of differing polarity, and responsively inhibiting said arc fault detection for a second predetermined time; and

(e) determining whether said (c) ignoring and said (d) determining are not met, and responsively indicating that at least one of said half-cycles of current having a peak amplitude greater than or equal to said predetermined amount is a parallel arc.

13. The method of claim 12 further comprising

counting occurrences of said parallel arc, which are each separated from one another by no more than a third predetermined time;

and

indicating a parallel arc fault in response to a predetermined plurality of said occurrences of said parallel arc, which are each separated from one another by no more than said third predetermined time.

14. The method of claim 13 further comprising

employing about 0.5 seconds as said third predetermined time.

15. The method of claim 13 further comprising

tripping open separable contacts responsive to said indicating a parallel arc fault.

16. The method of claim 12 further comprising

employing about 50 A peak as said predetermined amount.

17. The method of claim 12 further comprising

determining both of said (i) whether a first predetermined plurality of said half-cycles of current occur in succession and have non-unity power factor, and said whether a second predetermined plurality of said half-cycles of current occur in succession and each of said (ii) second predetermined plurality of said half-cycles of current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of current of like polarity or of differing polarity.

18. The method of claim 12 further comprising

employing about four as said first predetermined plurality.

19. The method of claim 12 further comprising

employing about 0.3 seconds as said first predetermined time.

20. The method of claim 12 further comprising

employing at least three as said second predetermined plurality.

21. The method of claim 12 further comprising

employing about 0.3 seconds as said second predetermined time.

22. The method of claim 12 further comprising

determining said (i) whether a first predetermined plurality of said half-cycles of current occur in succession and have non-unity power factor, in order to distinguish a motor start inrush current transient from a parallel arc fault.

23. The method of claim 12 further comprising

determining said (ii) whether a second predetermined plurality of said half-cycles of current occur in succession and each of said second predetermined plurality of said half-cycles of current has a smaller peak amplitude than that of an immediately preceding one of said half-cycles of current of like polarity or of differing polarity, in order to distinguish an incandescent dimmer inrush current from a parallel arc fault.

24. The method of claim 12 further comprising

employing a voltage having a voltage zero crossing;

and

for each of said half-cycles, determining if said current flowing in said power circuit at the voltage zero crossing has a different polarity than said current flowing in said power circuit about 90°

degrees after said voltage zero crossing, and responsively indicating a non-unity power factor.

25. The method of claim 12 further comprising

employing a voltage having a voltage zero crossing;

for each of said half-cycles, sensing said voltage about 90°

degrees after said voltage zero crossing; and

for each of said half-cycles, determining if said current flowing in said power circuit at said voltage zero crossing has a different polarity than said sensed voltage about 90°

degrees after said voltage zero crossing, and responsively indicating a non-unity power factor.

26. The method of claim 12 further comprising

incrementing an arc fault tally responsive to said parallel arc;

setting an arc fault detection timer to a third predetermined time; and

determining whether said arc fault tally is greater than a predetermined value and whether said arc fault detection timer has not expired and responsively indicating that a parallel arc fault has occurred.

27. The method of claim 26 further comprising

clearing said arc fault tally responsive to expiration of said arc fault detection timer.