ACTIVE MATRIX BACKPLANES ALLOWING RELAXED ALIGNMENT TOLERANCE

• US 20080205010A1
• Filed: 02/26/2007
• Published: 08/28/2008
• Est. Priority Date: 02/26/2007
• Status: Abandoned Application

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Haase, Michael A.
• Application Number:
  US11/678,865
• Publication Number:
  US 20080205010A1
• Time in Patent Office: Days
• US Class Current: 361/763
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

Backplanes for display devices and systems incorporating such backplanes are described. Pixel electrodes are disposed in an array of rows and columns on a substrate. The pixel electrodes may include electrode extensions. Data lines having a substantially constant width are arranged in relation to the pixel electrodes. Enable lines are configured to carry signals that control current flow between the data lines and the pixel electrodes. Each enable line has a substantially constant width and crosses a row of pixel electrodes and electrode extensions. The backplane design may include storage capacitors at the crossings of the enable lines and the pixel electrodes.

Claims

1. A display backplane, comprising:

pixel electrodes arranged in an array of rows and columns on a substrate, the pixel electrodes comprising electrode extensions;

branchless data lines, each data line having a substantially constant width;

enable lines configured to carry signals that control current flow between the data lines and the pixel electrodes, each enable line having a substantially constant width and crossing a row of pixel electrodes and electrode extensions; and

storage capacitors at the crossings of the enable lines and the pixel electrodes.

2. The display backplane of claim 1, wherein the substrate comprises a flexible, polymeric substrate.

3. The display backplane of claim 1, wherein the backplane comprises variation in alignment of the enable lines and electrode extensions, the variation in alignment related to distortion of the substrate during fabrication.

4. The display backplane of claim 1, wherein a length of the electrode extensions is more than three times a width of the enable lines.

5. The display backplanes of claim 1, wherein each electrode extension extends in a direction of a column and along a major portion of a next pixel electrode in the column.

6. The display backplane of claim 1, further comprising transistors configured to allow the current flow between the data lines and the pixel electrodes responsive to the signals on the enable lines.

7. The display backplane of claim 6, wherein the transistors comprise ZnO.

8. The display backplane of claim 6, wherein the enable lines form anodized aluminum gates of the transistors.

9. The display backplane of claim 6, wherein:

the data lines form source or drain electrodes of the transistors; and

the electrode extensions form the drain or source electrodes of the transistors.

10. The display backplane of claim 6, wherein source or drain electrodes of the transistors have a width greater than the width of the enable lines.

11. A display backplane, comprising:

pixel electrodes including electrode extensions arranged on a substrate; and

enable lines configured to carry signals that control current flow to the pixel electrodes, each enable line crossing one or more electrode extensions, each electrode extension having a length greater than about three times a width of the enable line at a crossing of the enable line and the electrode extension.

12. The display backplane of claim 11, wherein the pixel electrodes are arranged in columns and an electrode extension of a first pixel electrode of a column extends along an edge of an adjacent pixel electrode of the column.

13. The display backplane of claim 11, wherein variation in alignment of the enable lines and the electrode extensions is related to distortion of the substrate during fabrication.

14. The display backplane of claim 11, wherein the substrate comprises a flexible, polymeric substrate.

15. The display backplane of claim 11, wherein the enable lines have substantially constant width.

16. The display backplane of claim 11, further comprising:

data lines crossing the enable lines; and

transistors configured to allow the current flow between the data lines and the pixel electrodes responsive to the signals on the enable lines.

17. The display backplane of claim 16, wherein the data lines have substantially constant width.

18. The display backplane of claim 11, wherein the enable lines cross the pixel electrodes.

19. The display backplane of claim 18, further comprising storage capacitors at crossings of the enable lines and the pixel electrodes.

20. A display backplane, comprising:

one or more rows of pixel electrodes arranged on a substrate;

data lines arranged substantially perpendicular to the row of pixel electrodes;

branchless enable lines, each enable line crossing the pixel electrodes of a row across a major dimension of the pixel electrodes; and

transistors configured to allow current flow between the data lines and pixel electrodes.

21. The display backplane of claim 20, wherein the substrate comprises a flexible substrate.

22. The display backplane of claim 20, wherein the substrate comprises a polymeric substrate.

23. The display backplane of claim 20, wherein the transistors comprise ZnO.

24. The display backplane of claim 20, wherein:

the enable lines form anodized aluminum gates of the transistors;

the data lines form source or drain electrodes of the transistors; and

the pixel electrodes form the drain or source electrodes of the transistors.

25. The display backplane of claim 20, wherein one or both of the source or drain electrodes of the transistors have a width greater than the width of the enable line.

26. The display backplane of claim 20, wherein the pixel electrodes include electrode extensions that form electrodes of the transistors.

27. A display backplane, comprising:

at least one column of pixel electrodes arranged on a substrate, the pixel electrodes having electrode extensions; and

enable lines configured to carry signals that control current flow to the pixel electrodes, each enable line crossing at least one electrode extension in the column, alignment of the enable lines with respect to the electrode extensions varying with position along the column of pixel electrodes.

28. The display backplane of claim 27, wherein the enable lines have a substantially constant width.

29. The display backplane of claim 27, wherein the substrate comprises a flexible substrate.

30. The display backplane of claim 27, wherein the variation in alignment is related to distortion of the substrate during fabrication of the display backplane.

31. The display backplane of claim 27, wherein each pixel electrode comprises an electrode extension that crosses an enable line.

32. The display backplane of claim 31, wherein a length of the electrode extension is related to alignment tolerance of the display backplane due to substrate distortion.

33. A display backplane, comprising:

pixel electrodes arranged in columns, each pixel electrode having a major portion and one or more electrode extensions, at least one pixel electrode in a column having an electrode extension that extends in the direction of the column along at least a portion of an edge of a major portion of a next pixel electrode in the column; and

enable lines that cross the electrode extensions, the enable lines configured to carry signals that control data flow between data lines and the pixel electrodes.

34. The display backplane of claim 33, wherein a length of each electrode extension is related to alignment tolerance of the display backplane due to substrate distortion.

35. The display backplane of claim 33, wherein variation in alignment with respect to the electrode extensions is related to distortion of the substrate during fabrication.

36. The display backplane of claim 33, wherein the substrate comprises a flexible substrate.

37. The display backplane of claim 33, wherein the enable lines have substantially constant width.

38. The display backplane of claim 33, further comprising:

data lines crossing the enable lines; and

transistors configured to allow current flow between the data line and the pixel electrodes responsive to the signals on the enable lines.

39. The display backplane of claim 38, wherein the data lines have substantially constant width.

40. The display backplane of claim 33, wherein the enable lines cross the pixel electrodes.

41. The display backplane of claim 40, further comprising storage capacitors at crossings of the enable lines and the pixel electrodes.

42. A display backplane, comprising:

pixel electrodes including electrode extensions arranged in a matrix on a substrate;

data lines;

enable lines crossing the pixel electrodes and the data lines;

one or more semiconductor regions, the semiconductor regions having areas larger than a pitch of the pixel electrodes, the semiconductor regions configured to allow current flow between the data lines and the pixel electrodes; and

storage capacitors at the crossings of the enable lines and the pixel electrodes, wherein voltages on the data lines are adjusted to compensate for crosstalk between the data lines.

43. The display backplane of claim 42, wherein the semiconductor regions comprise regional transistors having areas of channel formation controlled by signals on the enable lines.

45. A display device, comprising:

a backplane, comprising;

pixel electrodes including electrode extensions arranged in an array of rows and columns on a substrate;

data lines, each data line having a substantially constant width;

enable lines configured to carry signals that control data flow from the data lines to the pixel electrodes, each enable line having a substantially constant width and crossing a row of pixel electrodes and electrode extensions; and

storage capacitors at the crossings of the enable lines and the pixel electrodes; and

pixels comprising an optically active material coupled to the pixel electrodes.

46. The display device of claim 45, wherein the optically active material comprises a liquid crystal material.

47. The display device of claim 45, wherein the optically active material comprises an electrochromic material.

48. The display device of claim 45, wherein the optically active material comprises an electrophoretic material.

49. The display device of claim 45, wherein the display device comprises a reflective display device.

50. The display device of claim 45, wherein the pixels comprise color pixels and a common enable line crosses pixel electrodes of like color pixels.

51. The display of claim 45, wherein the pixels comprise color pixels and a common data line is associated with like color pixels.

52. A display device, comprising:

a backplane, comprising;

one or more rows of pixel electrodes arranged on a substrate;

data lines arranged substantially perpendicular to the row of pixel electrodes;

branchless enable lines, each enable line crossing the pixel electrodes of a row across a major dimension of the pixel electrodes; and

transistors configured to allow current flow between the data lines and pixel electrodes; and

pixels comprising an optically active material coupled to the pixel electrodes.

53. The display device of claim 52, wherein the optically active material comprises an electrophoretic material.