NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20080205119A1
• Filed: 12/10/2007
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Nakayama, Masayoshi, NAGAI, Hiroyasu
• Granted Patent: US 7,561,461 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

In order to determine data stored in a memory cell of a resistive cross-point cell array, two reference cells having two different known resistance values (e.g., data “0” and data “1”) are provided, and a difference in current between a selected cell and the reference cell having data “0” and a difference in current between the selected cell and the reference cell having data “1” are compared. By comparison with a current of the reference cell which has a parasitic current as with the selected cell and has known data “0”/“1”, data can be determined while suppressing an influence of a parasitic current.

Claims

1. A non-volatile semiconductor memory device comprising:

a cross-point cell array;

a plurality of word lines extended in a first direction;

a plurality of bit lines extended in a second direction different from the first direction;

a first decoding circuit for selecting a selected word line from the plurality of word lines;

a second decoding circuit for selecting a selected bit line from the plurality of bit lines;

a first reference signal generating circuit for generating a first reference signal;

a second reference signal generating circuit for generating a second reference signal different from the first reference signal; and

a read circuit,

wherein the cross-point cell array includes a plurality of cells,

each of the plurality of cells is interposed between one of the plurality of word lines and one of the plurality of bit lines,

a selected cell is interposed between the selected word line and the selected bit line,

based on a detection signal corresponding to a detection current which is caused to flow through the selected bit line by applying a voltage between the selected word line and the selected bit line, the read circuit compares a first difference signal corresponding to a difference between the detection signal and the first reference signal with a second difference signal corresponding to a difference between the detection signal and the second reference signal, thereby determining data stored in the selected cell.

2. The non-volatile semiconductor memory device of claim 1, wherein

the first reference signal generating circuit is a first reference cell interposed between a first reference word line and a first reference bit line,

the first reference signal is a current caused to flow through the first reference bit line by applying a voltage between the first reference word line and the first reference bit line,

the second reference signal generating circuit is a second reference cell interposed between a second reference word line and a second reference bit line, and

the second reference signal is a current caused to flow through the second reference bit line by applying a voltage between the second reference word line and the second reference bit line.

3. The non-volatile semiconductor memory device of claim 2, wherein

the first reference cell is a cell having a first resistance value, and the second reference cell is a cell having a second resistance value different from the first resistance value.

4. The non-volatile semiconductor memory device of claim 2, wherein

the first reference cell and the second reference cell are provided in the cross-point cell array.

5. The non-volatile semiconductor memory device of claim 4, wherein

the selected word line, the first reference word line, and the second reference word line are the same word line.

6. The non-volatile semiconductor memory device of claim 4, wherein

the first reference bit line is one of the plurality of bit lines, and the second reference bit line is another one of the plurality of bit lines.

7. The non-volatile semiconductor memory device of claim 6, wherein

the sum of resistance values of reference cells on the first reference bit line and the sum of resistance values of reference cells on the second reference bit line are substantially the same.

8. The non-volatile semiconductor memory device of claim 4, wherein

the first reference bit line and the second reference bit line are different bit lines of the plurality of bit lines.

9. The non-volatile semiconductor memory device of claim 4, wherein

the first reference bit line and the second reference bit line are adjacent bit lines of the plurality of bit lines.

10. The non-volatile semiconductor memory device of claim 4, wherein

the first reference cell and the second reference cell are located at substantially a center portion of the cross-point cell array or at substantially a center portion of a cell array to be read.

11. The non-volatile semiconductor memory device of claim 2, wherein

the first decoding circuit applies a voltage to the selected word line and the first reference word line during a first read operation period, and applies a voltage to the selected word line and the second reference word line during a second read operation period delayed in time from the first read operation period.

12. The non-volatile semiconductor memory device of claim 2, wherein

the first decoding circuit applies a voltage to the selected word line, the first reference word line, and the second reference word line.

13. The non-volatile semiconductor memory device of claim 2, wherein

the second decoding circuit applies a voltage to the selected bit line and the first reference bit line during a first read operation period, and applies a voltage to the selected bit line and the second reference bit line during a second read operation period delayed in time from the first read operation period.

14. The non-volatile semiconductor memory device of claim 2, wherein

the second decoding circuit applies a voltage to the selected bit line, the first reference bit line, and the second reference bit line.

15. The non-volatile semiconductor memory device of claim 1, wherein

the read circuit includes:

a difference signal generating circuit for generating the first difference signal corresponding to the difference between the detection signal and the first reference signal during a first read operation period, and generating the second difference signal corresponding to the difference between the detection signal and the second reference signal during a second read operation period delayed in time from the first read operation period;

a reference signal selecting circuit for connecting the first reference signal generating circuit to the difference signal generating circuit during the first read operation period, and connecting the second reference signal generating circuit to the difference signal generating circuit during the second read operation period;

a difference signal holding circuit for holding the first difference signal during the first read operation period; and

a data determining circuit for comparing the first difference signal held by the difference signal holding circuit with the second difference signal during the second read operation period, thereby determining data stored in the selected cell.

16. The non-volatile semiconductor memory device of claim 1, wherein

the read circuit includes:

a first difference signal generating circuit for generating the first difference signal corresponding to the difference between the detection signal and the first reference signal;

a second difference signal generating circuit for generating the second difference signal corresponding to the difference between the detection signal and the second reference signal; and

a data determining circuit for comparing the first difference signal with the second difference signal, thereby determining data stored in the selected cell.

17. A non-volatile semiconductor memory device comprising:

a cross-point cell array;

a plurality of word lines extended in a first direction;

a plurality of bit lines extended in a second direction different from the first direction;

a first decoding circuit for selecting a selected word line from the plurality of word lines;

a second decoding circuit for selecting a selected bit line from the plurality of bit lines;

a first reference signal generating circuit for generating a first reference signal;

a second reference signal generating circuit for generating a second reference signal different from the first reference signal; and

a read circuit for determining data stored in a selected cell based on a detection signal corresponding to a detection current flowing through the selected bit line,

wherein the read circuit includes;

a difference signal generating circuit for generating a difference signal corresponding to a difference between two different signals; and

a reference signal selecting circuit for connecting the first reference signal generating circuit to the difference signal generating circuit during a first read operation period, and connecting the second reference signal generating circuit to the difference signal generating circuit during a second read operation period delayed in time from the first read operation period, and

the read circuit connects the selected bit line via the second decoding circuit to the difference signal generating circuit and the first reference signal generating circuit to the difference signal generating circuit during the first read operation period, and connects the selected bit line via the second decoding circuit to the difference signal generating circuit and the second reference signal generating circuit to the difference signal generating circuit during the second read operation period.

18. The non-volatile semiconductor memory device of claim 17, wherein

the second decoding circuit is provided with a function of the reference signal selecting circuit.

19. A non-volatile semiconductor memory device comprising:

a cross-point cell array;

a plurality of word lines extended in a first direction;

a plurality of bit lines extended in a second direction different from the first direction;

a first decoding circuit for selecting a selected word line from the plurality of word lines;

a second decoding circuit for selecting a selected bit line from the plurality of bit lines;

a first reference signal generating circuit for generating a first reference signal;

a second reference signal generating circuit for generating a second reference signal different from the first reference signal; and

a read circuit for determining data stored in a selected cell based on a detection signal corresponding to a detection current flowing through the selected bit line,

wherein the read circuit includes;

a first difference signal generating circuit for generating a first difference signal corresponding to a difference between the detection signal and the first reference signal; and

a second difference signal generating circuit for generating a second difference signal corresponding to a difference between the detection signal and the second reference signal, and

the read circuit connects the selected bit line via the second decoding circuit to the first difference signal generating circuit and the first reference signal generating circuit to the first difference signal generating circuit, and connects the selected bit line via the second decoding circuit to the second difference signal generating circuit and the second reference signal generating circuit to the second difference signal generating circuit.