SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME

• US 20080205137A1
• Filed: 07/16/2007
• Published: 08/28/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hara, Takahiko, Yanagidaira, Kosuke, Fukuda, Koicho
• Granted Patent: US 7,652,928 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.

Claims

1. A semiconductor memory device comprising:

a memory cell array;

a voltage generating circuit;

a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter; and

a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.

2. The device according to claim 1, further comprising:

a plurality of parameter registers in which the reference pulse number of the advance-write voltage and the parameter, which are read out from the memory circuit, are set.

3. The device according to claim 1, further comprising:

a plurality of cache memories into which the reference pulse number of the advance-write voltage and the parameter are read out batchwise from the memory circuit.

4. The device according to claim 1, wherein the control circuit controls, when the pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to increase a program verify level in accordance with the parameter.

5. The device according to claim 1, wherein the reference pulse number of the advance-write voltage and the parameter are stored in association with each of erase units, each of read units or each of write units of the memory cell array.

6. The device according to claim 1, further comprising:

an arithmetic circuit which determines the parameter of a write operation on the basis of the reference pulse number.

7. The device according to claim 6, wherein the arithmetic circuit comprises a first deterioration information detection circuit which detects first deterioration information on the basis of the reference pulse number and a write pulse number.

8. The device according to claim 7, wherein the memory circuit further stores a reference voltage and a voltage correction amount, and

the arithmetic circuit further comprises a first shift amount determination circuit which determines a shift amount of the initial value of the write voltage on the basis of the first deterioration information, the reference voltage and the voltage correction amount.

9. The device according to claim 6, wherein the memory circuit further stores a reference pulse number which determines whether or not to shift the step-up width, and

the arithmetic circuit further comprises a second deterioration information detection circuit which detects second deterioration information on the basis of the reference pulse number which determines whether or not to shift the step-up width, and the write pulse number.

10. The device according to claim 9, wherein the memory circuit further stores a reference voltage of the step-up width and a voltage correction amount of the step-up width, and

the arithmetic circuit further comprises a second shift amount determination circuit which determines a shift amount of the step-up width of the write voltage on the basis of the second deterioration information, the reference voltages of the step-up width and the voltage correction amounts of the step-up width.

11. A semiconductor memory device capable of storing multi-bit data in one memory cell, comprising:

a memory cell array in which the memory cell is disposed;

a voltage generating circuit;

a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter; and

a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.

12. The device according to claim 11, further comprising:

a plurality of parameter registers in which the reference pulse number of the advance-write voltage and the parameter, which are read out from the memory circuit, are set.

13. The device according to claim 11, further comprising:

a plurality of cache memories into which the reference pulse number of the advance-write voltage and the parameter are read out batchwise from the memory circuit.

14. The device according to claim 11, wherein the control circuit controls, when the pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to increase a program verify level in accordance with the parameter.

15. The device according to claim 11, further comprising:

an arithmetic circuit which determines the parameter of a write operation on the basis of the reference pulse number.

16. The device according to claim 15, wherein the memory circuit further stores a reference voltage and a voltage correction amount, and

the arithmetic circuit comprises:

a first deterioration information detection circuit which detects first deterioration information on the basis of the reference pulse number and a write pulse number; and

a first shift amount determination circuit which determines a shift amount of the initial value of the write voltage on the basis of the first deterioration information, the reference voltage and the voltage correction amount.

17. The device according to claim 16, wherein the memory circuit further stores a reference pulse number which determines whether or not to shift the step-up width, a reference voltage of the step-up width and a voltage correction amount of the step-up width, and the arithmetic circuit further comprises a second deterioration information detection circuit which detects second deterioration information on the basis of the reference pulse number which determines whether or not to shift the step-up width, and the write pulse number;

and

a second shift amount determination circuit which determines a shift amount of the step-up width of the write voltage on the basis of the second deterioration information, the reference voltages of the step-up width and the voltage correction amounts of the step-up width.

18. A control method of a semiconductor memory device including a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls the voltage generating circuit, the method comprising:

causing the control circuit to execute an erase operation in the memory cell array;

counting a pulse number of pulses of an advance-write voltage which is applied to the memory cell array after the erase operation, thereby detecting deterioration information of the memory cell array;

changing, when a write operation is executed in the memory cell array, the parameter in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in a case where the counted pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage; and

controlling the voltage generating circuit and executing the write operation by using the changed parameter.

19. The control method according to claim 18, wherein the device is capable of storing multi-bit data in one memory cell which is disposed in the memory cell array, and the device further comprises an arithmetic circuit which determines a parameter of the write operation on the basis of the reference pulse number.