Bit line structure for a multilevel, dual-sided nonvolatile memory cell array

• US 20080205140A1
• Filed: 02/08/2008
• Published: 08/28/2008
• Est. Priority Date: 02/26/2007
• Status: Abandoned Application

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Hsu, Fu-Chang, Lee, Peter
• Application Number:
  US12/069,228
• Publication Number:
  US 20080205140A1
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columnar bit line structure such that each column of the dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells.

Claims

1. A nonvolatile memory array comprising:

a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns wherein said dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping of dual-sided charge-trapping nonvolatile memory cells that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor;

a plurality of bit lines, connected such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines, such that a source/drain of said top select transistor is connected to a first of said associated pair of bit lines and a source/drain of said bottom select transistor is connected to a second of said associated pair of bit lines and such that said first of said associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and said second of said associated pair of bit lines is further associated with a second adjacent column of said dual-sided charge-trapping nonvolatile memory cells, wherein a source/drain of said top select transistor of said first adjacent column is connected to said second of said associated pair of bit lines and a source/drain of said bottom select transistor of said second adjacent column is connected to said first of said associated pair of bit lines; and

a bit line controller connected to said plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.

2. The nonvolatile memory array of claim 1 further comprising:

a plurality of word lines, each word line associated with one row of said plurality of dual-sided charge-trapping nonvolatile memory cells;

a plurality of top select lines, each top select line connected to a gate of said top select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells;

a plurality of bottom select lines, each bottom select line connected to a gate of said bottom select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and

a word line controller connected to said word lines, said top select lines, and said bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing said trapped charges representing said multiple digital data bits within said charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.

3. The nonvolatile memory array of claim 2 wherein said bit line controller comprises:

a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits through said first of said associated pair of bit lines to said source/drain of said top select transistor to a first drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region; and

a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region.

4. The nonvolatile memory array of claim 2 wherein said word line controller comprises:

a word line program voltage source that provides a very large program voltage for generating a voltage field between a control gate of said selected dual-sided charge-trapping nonvolatile memory cells and a channel region of said selected dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a charge trapping region of said selected dual-sided charge-trapping nonvolatile memory cell.

5. The nonvolatile memory array of claim 2 wherein said word line controller comprises:

a first select line program voltage source that selectively provides a moderately large select voltage to be transferred on said top select lines to activate said top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and

a second select line program voltage source that selectively provides said moderately large select voltage to be transferred on said bottom select lines to activate said bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells.

6. The nonvolatile memory array of claim 2 wherein:

said word line controller comprises;

a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of said selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of said plurality of threshold adjustment voltages representative of said portion of multiple digital data bits; and

said bit line controller comprises;

a read drain voltage generator that generates a drain voltage level that is selectively transferred through said first and second of said paired bit lines to said first drain/source and the second drain/source to activate said selected dual-sided charge-trapping nonvolatile memory cells dependent upon a trapped charge level within said charge trapping region;

a first ground reference voltage generator to generate a ground reference voltage transferred selectively transferred through said first and second of said paired bit lines to said first and second drain/sources; and

a sensing circuit connected through said pairs of bit lines to said selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of said charge trapping region representing said multiple digital data bits through said first and second of said paired bit lines.

7. The nonvolatile memory array of claim 2 wherein:

said word line controller comprises;

a word line erase voltage source that provides a very large erase voltage for generating a voltage field between said channel region of said dual-sided charge-trapping nonvolatile memory cell and said control gate of said dual-sided charge-trapping nonvolatile memory cell to inject hot carriers to said charge trapping region to be extracted from the channel region of said dual-sided charge-trapping nonvolatile memory cell; and

said bit line controller comprises;

a second ground reference voltage generator to apply said ground reference voltage to said first and second drain/sources.

8. The nonvolatile memory array of claim 4 wherein said dual-sided charge-trapping nonvolatile memory cell is an n-channel memory cell.

9. The nonvolatile memory array of claim 8 wherein said very large program voltage has a level of from approximately −

6.0V to approximately −

10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.

10. The nonvolatile memory array of claim 8 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.

11. The nonvolatile memory array of claim 6 wherein said plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.

12. The nonvolatile memory array of claim 11 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.

13. The nonvolatile memory array of claim 7 wherein said very large erase voltage has voltage level of from approximately +15.0V to approximately +20V to increase said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.

14. The nonvolatile memory array of claim 4 wherein said dual-sided charge-trapping nonvolatile memory cell is a p-channel memory cell.

15. The nonvolatile memory array of claim 14 wherein said medium large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.

16. The nonvolatile memory array of claim 14 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately −

1.0V to approximately −

6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.

17. The nonvolatile memory array of claim 6 wherein said plurality of threshold detection voltages have a voltage range from approximately −

2.0V to approximately −

5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.

18. The nonvolatile memory array of claim 17 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.

19. The nonvolatile memory array of claim 14 wherein said very large erase voltage has voltage level of from approximately −

15.0V to approximately −

20V to decrease said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.

20. A nonvolatile memory integrated circuit comprising:

an array of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns wherein said dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping of dual-sided charge-trapping nonvolatile memory cells that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor;

a plurality of bit lines, connected such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines, such that a source/drain of said top select transistor is connected to a first of said associated pair of bit lines and a source/drain of said bottom select transistor is connected to a second of said associated pair of bit lines and such that said first of said associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and said second of said associated pair of bit lines is further associated with a second adjacent column of said dual-sided charge-trapping nonvolatile memory cells, wherein a source/drain of said top select transistor of said first adjacent column is connected to said second of said associated pair of bit lines and a source/drain of said bottom select transistor of said second adjacent column is connected to said first of said associated pair of bit lines;

a plurality of word lines, each word line connected to control gates of all said dual-sided charge-trapping nonvolatile memory cells of one of said rows of said array of said plurality dual-sided charge-trapping nonvolatile memory cells;

a plurality of top select lines, each top select line connected to a gate of said top select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells;

a plurality of bottom select lines, each bottom select line connected to a gate of said bottom select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells;

a bit line controller connected to said plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells; and

a word line controller connected to said word lines, said top select lines, and said bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing said trapped charges representing said multiple digital data bits within said charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.

21. The nonvolatile memory integrated circuit of claim 20 wherein said word line controller comprises:

a word line program voltage source that provides a very large program voltage for generating a voltage field between a control gate of said dual-sided charge-trapping nonvolatile memory cell and a channel region of said dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a charge trapping region of said dual-sided charge-trapping nonvolatile memory cell.

22. The nonvolatile memory integrated circuit of claim 20 wherein said bit line controller comprises:

a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits to a first drain/source of said nonvolatile memory cell array to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region; and

a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said nonvolatile memory cell array to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region.

23. The nonvolatile memory integrated circuit of claim 21 wherein said word line controller further comprises:

a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of said selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of said plurality of threshold adjustment voltages representative of said portion of multiple digital data bits;

24. The nonvolatile memory integrated circuit of claim 21 wherein said bit line controller further comprises:

a read drain voltage generator that generates a drain voltage level that is selectively transferred through said first and second of said paired bit lines to first drain/source and the second drain/source to activate said selected dual-sided charge-trapping nonvolatile memory cell dependent upon a trapped charge level within said charge trapping region;

a first ground reference voltage generator to generate a ground reference voltage transferred through said first and second of said paired bit lines to said first and second drain/sources; and

a sensing circuit connected through said pairs of bit lines to said selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of said charge trapping region representing said multiple digital data bits through said first and second of said paired bit lines.

25. The nonvolatile memory integrated circuit of claim 23 wherein said word line controller further comprises:

a word line erase voltage source connected through said word lines to said selected dual-sided charge-trapping nonvolatile memory cells that provides a very large erase voltage for generating a voltage field between said channel region of said selected dual-sided charge-trapping nonvolatile memory cells and said control gate of said selected dual-sided charge-trapping nonvolatile memory cells to inject hot carriers to said charge trapping region to be extracted from the channel region of said selected dual-sided charge-trapping nonvolatile memory cells.

26. The nonvolatile memory integrated circuit of claim 25 wherein said bit line controller comprises:

a second ground reference voltage generator to apply said ground reference voltage to said first and second drain/sources.

29. The nonvolatile memory integrated circuit of claim 22 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.

30. The nonvolatile memory integrated circuit of claim 23 wherein said plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.

31. The nonvolatile memory integrated circuit of claim 30 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.

32. The nonvolatile memory integrated circuit of claim 25 wherein said very large erase voltage has voltage level of from approximately +15.0V to approximately +20V to increase said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.

33. The nonvolatile memory integrated circuit of claim 20 wherein each of said plurality dual-sided charge-trapping nonvolatile memory cells is a p-channel memory cell.

34. The nonvolatile memory integrated circuit of claim 33 wherein said medium large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.

35. The nonvolatile memory integrated circuit of claim 22 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately −

1.0V to approximately −

6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.

36. The nonvolatile memory integrated circuit of claim 23 wherein said plurality of threshold detection voltages have a voltage range from approximately −

2.0V to approximately −

5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.

37. The nonvolatile memory integrated circuit of claim 36 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.

38. The nonvolatile memory integrated circuit of claim 25 wherein said very large erase voltage has voltage level of from approximately −

15.0V to approximately −

20V to decrease said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.

27. The nonvolatile memory integrated circuit 21 wherein each of said plurality dual-sided charge-trapping nonvolatile memory cells is an n-channel memory cell.

28. The nonvolatile memory integrated circuit of claim 27 wherein said very large program voltage has a level of from approximately −

6.0V to approximately −

10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.

39. A method for forming a nonvolatile memory array comprising the steps of:

providing a plurality of dual-sided charge-trapping nonvolatile memory cells;

arranging said plurality of dual-sided charge-trapping nonvolatile memory cells in rows and columns

forming said dual-sided charge-trapping nonvolatile memory cells on each column into at least one grouping of dual-sided charge-trapping nonvolatile memory cells;

arranging said connecting into a NAND series string of dual-sided charge-trapping nonvolatile memory cells, each NAND series string having a top select transistor and a bottom select transistor;

connecting a plurality of bit lines, such that each column of the dual-sided charge-trapping nonvolatile memory cells is associated with a pair of bit lines, such that a source/drain of said top select transistor is connected to a first of said associated pair of bit lines and a source/drain of said bottom select transistor is connected to a second of said associated pair of bit lines and such that said first of said associated pair of bit lines is further associated with a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and said second of said associated pair of bit lines is further associated with a second adjacent column of said dual-sided charge-trapping nonvolatile memory cells, wherein a source/drain of said top select transistor of said first adjacent column is connected to said second of said associated pair of bit lines and a source/drain of said bottom select transistor of said second adjacent column is connected to said first of said associated pair of bit lines; and

connecting a bit line controller to said plurality of bit lines to transfer bit line operational voltages to selected dual-sided charge-trapping nonvolatile memory cells for programming, reading, and erasing trapped charges representing multiple digital data bits within a charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.

40. The method for forming said nonvolatile memory array of claim 39 further comprising the steps of:

providing a plurality of word lines;

connecting each word line with one row of said plurality of dual-sided charge-trapping nonvolatile memory cells;

providing a plurality of top select lines;

connecting each top select line to a gate of said top select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells;

providing a plurality of bottom select lines;

connecting each bottom select line to a gate of said bottom select transistor of at least one of said NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and

connecting a word line controller to said word lines, said top select lines, and said bottom select lines to transfer word line operational voltages for selecting, programming, reading, and erasing said trapped charges representing said multiple digital data bits within said charge trapping region of each of said selected dual-sided charge-trapping nonvolatile memory cells.

41. The method for forming said nonvolatile memory array of claim 39 wherein said bit line controller comprises:

a first bit line program voltage source that provides one of a plurality of threshold adjustment voltages representing a portion of said multiple digital data bits through said first of said associated pair of bit lines to said source/drain of said top select transistor to a first drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a first level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region; and

a second bit line program voltage source that provides a second of said plurality of threshold adjustment voltages representing another portion of said multiple digital data bits to a second drain/source of said selected dual-sided charge-trapping nonvolatile memory cells to set a second level of said hot carrier charge representing said portion of said multiple digital data bits to charge trapping region.

42. The method for forming said nonvolatile memory array of claim 39 wherein said word line controller comprises:

a word line program voltage source that provides a very large program voltage for generating a voltage field between a control gate of said selected dual-sided charge-trapping nonvolatile memory cells and a channel region of said selected dual-sided charge-trapping nonvolatile memory cell to extracted hot carriers from said channel region to be injected into a charge trapping region of said selected dual-sided charge-trapping nonvolatile memory cell.

43. The method for forming said nonvolatile memory array of claim 39 wherein said word line controller comprises:

a first select line program voltage source that selectively provides a moderately large select voltage to be transferred on said top select lines to activate said top select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells; and

a second select line program voltage source that selectively provides a moderately large select voltage to be transferred on said bottom select lines to activate said bottom select transistors of selected NAND series strings of dual-sided charge-trapping nonvolatile memory cells.

44. The method for forming said nonvolatile memory array of claim 39 wherein:

said word line controller further comprises;

a word line read voltage source that generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages of said selected dual-sided charge-trapping nonvolatile memory cells resulting from a selected one of said plurality of threshold adjustment voltages representative of said portion of multiple digital data bits; and

said bit line controller further comprises;

a read drain voltage generator that generates a drain voltage level that is selectively transferred through said first and second of said paired bit lines to said first drain/source and the second drain/source to activate said selected dual-sided charge-trapping nonvolatile memory cells dependent upon a trapped charge level within said charge trapping region;

a first ground reference voltage generator to generate a ground reference voltage transferred selectively transferred through said first and second of said paired bit lines to said first and second drain/sources; and

a sensing circuit connected through said pairs of bit lines to said selected dual-sided charge-trapping nonvolatile memory cells to detect a programmed state of said charge trapping region representing said multiple digital data bits through said first and second of said paired bit lines.

45. The method for forming said nonvolatile memory array of claim 39 wherein:

said word line controller further comprises;

a word line erase voltage source that provides a very large erase voltage for generating a voltage field between said channel region of said dual-sided charge-trapping nonvolatile memory cell and said control gate of said dual-sided charge-trapping nonvolatile memory cell to inject hot carriers to said charge trapping region to be extracted from the channel region of said dual-sided charge-trapping nonvolatile memory cell; and

said bit line controller further comprises;

a second ground reference voltage generator to apply said ground reference voltage to said first and second drain/sources.

46. The method for forming said nonvolatile memory array of claim 42 wherein said dual-sided charge-trapping nonvolatile memory cell is an n-channel memory cell.

47. The method for forming said nonvolatile memory array of claim 46 wherein said very large program voltage has a level of from approximately −

6.0V to approximately −

10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.

48. The method for forming said nonvolatile memory array of claim 46 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately +1.0V to approximately +6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.

49. The nonvolatile memory array of claim 44 wherein said plurality of threshold detection voltages have a voltage range from approximately +2.0V to approximately +5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.

50. The method for forming said nonvolatile memory array of claim 49 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.

51. The method for forming said nonvolatile memory array of claim 45 wherein said very large erase voltage has voltage level of from approximately +15.0V to approximately +20V to increase said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.

52. The method for forming said nonvolatile memory array of claim 42 wherein said dual-sided charge-trapping nonvolatile memory cell is a p-channel memory cell.

53. The method for forming said nonvolatile memory array of claim 52 wherein said very large program voltage has a level of from approximately +6.0V to approximately +10.0V to cause said hot carrier injection to be a hot hole injection to said charge trapping layer.

54. The method for forming said nonvolatile memory array of claim 52 wherein said plurality of threshold adjustment voltages have a voltage range of from approximately −

1.0V to approximately −

6.0V divided into intervals sufficient to determine said first and second portion of said plurality of said multiple digital data bits.

55. The method for forming said nonvolatile memory array of claim 44 wherein said plurality of threshold detection voltages have a voltage range from approximately −

2.0V to approximately −

5.0V and are divided into increments that differentiate said plurality of programmed threshold voltages.

56. The method for forming said nonvolatile memory array of claim 55 wherein said drain voltage level must be a voltage level sufficient to overcome threshold voltages of said first and second charge trapping regions and not sufficient to cause soft writing of said dual-sided charge-trapping nonvolatile memory cell.

57. The method for forming said nonvolatile memory array of claim 52 wherein said very large erase voltage has voltage level of from approximately −

15.0V to approximately −

20V to decrease said threshold voltage of said dual-sided charge-trapping nonvolatile memory cell.