MEMORY CONTROLLER CONTROLLING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DEVICE

• US 20080205145A1
• Filed: 02/28/2008
• Published: 08/28/2008
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanno, Shinichi, Shirakihara, Toshio, Kuroda, Yosuke
• Granted Patent: US 7,796,429 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

Claims

1. A memory controller which controls a semiconductor storage device including nonvolatile memory cells, the controller comprising:

a generating circuit which generates a plurality of first data based on a second data to be collectively written in the memory cells, the second data having multi-bit; and

a selection circuit which retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells, the selection circuit selecting one of the plurality of first data, a selected first data having a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data, the selection circuit retaining the sum concerning the selected first data as the new cumulative value.

2. The controller according to claim 1, wherein the selected first data and information indicating the selected first data is collectively written in the memory cells connected to a same word line.

3. The controller according to claim 1, wherein the generating circuit generates a plurality of third data based on the second data, and the generating circuit generates the first data by encoding the third data according to a charge amount charged in the memory cells by each of the third data, and

one of the third data corresponding to the selected first data and information indicating the selected first data is collectively written in the memory cells connected to a same word line.

4. The controller according to claim 1, wherein the generating circuit includes an inverting circuit which inverts each bit of the second data, and the generating circuit outputs the non-inverting second data and the second data whose each bit is inverted by the inverting circuit as the first data.

5. The controller according to claim 1, wherein the generating circuit includes:

a creating circuit which creates a plurality of pseudo-random numbers; and

a logic gate which calculates an exclusive OR of each of the plurality of pseudo-random numbers and each bit of the second data to output a calculation result as the first data.

6. The controller according to claim 1, wherein the selection circuit selects one of the first data, in which a difference between a maximum value and a minimum value of each digit in the sum becomes a minimum.

7. The controller according to claim 1, wherein the selection circuit selects one of the first data, in which a standard deviation of each digit in the sum becomes a minimum.

8. The controller according to claim 1, wherein the selection circuit sets a result obtained by subtracting “

1”

from each digit of the sum to the new cumulative value when all the digits of the sum are at least “

1”

for the selected first data.

9. The controller according to claim 1, wherein, when one of the digits of the sum generates an overflow, the selection circuit replaces a value of the digit in which the overflow is generated by a quotient of “

2”

of a maximum value which is countable in the digit, and the selection circuit replaces each of other digits by the quotient of “

2”

.

11. A semiconductor device comprising:

a memory controller recited in claim 1; and

the semiconductor storage device which includes a first memory region and a second memory region, the memory cells being arranged in each of the first memory region and the second memory region, data corresponding to the first data selected by the selection circuit of the memory controller being written in the memory cells of the first memory region, the information indicating the selected first data being written in the memory cells of the second memory region.

12. The device according to claim 11, wherein the selected first data and information indicating the selected first data is collectively written in the memory cells connected to a same word line of the first and second memory regions, respectively.

13. The device according to claim 11, wherein the generating circuit generates a plurality of third data based on the second data, and the generating circuit generates the first data by encoding the third data according to a charge amount charged in the memory cells by each of the third data, and

one of the third data corresponding to the selected first data and information indicating the selected first data is collectively written in the memory cells connected to a same word line of the first and second memory regions, respectively.

14. The device according to claim 11, wherein the generating circuit includes an inverting circuit which inverts each bit of the second data, and the generating circuit outputs the non-inverting second data and the second data whose each bit is inverted by the inverting circuit as the first data.

15. The device according to claim 11, wherein the generating circuit includes:

a creating circuit which creates a plurality of pseudo-random numbers; and

a logic gate which calculates an exclusive OR of each of the plurality of pseudo-random numbers and each bit of the second data to output a calculation result as the first data.

16. The device according to claim 11, wherein the selection circuit selects one of the first data, in which a difference between a maximum value and a minimum value of each digit in the sum becomes a minimum.

17. The device according to claim 11, wherein the selection circuit selects one of the first data, in which a standard deviation of each digit in the sum becomes a minimum.

18. The device according to claim 11, wherein the selection circuit sets a result obtained by subtracting “

1”

from each digit of the sum to the new cumulative value when all the digits of the sum are at least “

1”

for the selected first data.

19. The device according to claim 11, wherein, when one of the digits of the sum generates an overflow, the selection circuit replaces a value of the digit in which the overflow is generated by a quotient of “

2”

of a maximum value which is countable in the digit, and the selection circuit replaces each of other digits by the quotient of “

2”

.

10. A memory controller which controls a semiconductor storage device including nonvolatile memory cells, the controller comprising:

a creating circuit which creates a pseudo-random number; and

a logic gate which calculates an exclusive OR of the pseudo-random number and each bit of multi-bit data which is to be written collectively in the memory cells connected to a same word line, the calculation result performed by the logic gate is written in the memory cells.