Local self-boost inhibit scheme with shielded word line

• US 20080205147A1
• Filed: 10/10/2007
• Published: 08/28/2008
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Incarnati, Michele, Santin, Giovanni
• Granted Patent: US 7,742,338 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of the set or pair to shield the other from word line to word line capacitive voltage coupling. In NAND memory string embodiments the various cells of strings of non-volatile memory cells are programmed utilizing modified or unmodified drain-side self boost, source-side self boost, local self boost, and virtual ground programming processes that utilize two or more “blocking” memory cells on either the source line side and drain line side of a selected memory cell. The paired blocking cells shield each other during programming to reduce coupled noise, to prevent charge leakage from the boosted channel of the selected memory cell.

Claims

1. A method of shielding word line capacitive coupling in memory devices, comprising:

applying a first voltage to a first word line in a memory array of a memory device;

applying the first voltage to one or more second word lines to capacitively shield the first word line, wherein the one or more second word lines are directly adjacent to the first word line; and

applying at least one third voltage to at least one or more third word lines, wherein the at least one or more second word lines are adjacent to the directly adjacent the first word line and one or more second word lines in the memory array.

2. The method of claim 1, wherein the memory device is a non-volatile memory device.

3. The method of claim 2, wherein the non-volatile memory device is one of a NOR architecture memory device, a NAND architecture memory device, and a virtual ground memory device and where the third voltage is an elevated programming voltage or an elevated erase voltage.

4. A method of programming a non-volatile NAND architecture memory string, comprising:

applying a program voltage to a selected word line coupled to a non-volatile memory cell of the NAND architecture memory string that is selected for programming;

applying an intermediate voltage to at least one set of two or more word lines, wherein the set of two or more word lines are directly adjacent to each other; and

applying a pass voltage to one or more remaining word lines between the set of one or more source-side adjacent word lines and the source line.

5. The method of claim 4, wherein the intermediate voltage is a cutoff voltage.

6. The method of claim 4, wherein the intermediate voltage is one of Vcc, Vss, and ground.

7. The method of claim 4, wherein the at least one set of two or more word lines are physically adjacent the selected word line.

8. The method of claim 4, wherein the method of programming is one of a local self boost programming operation, a modified local self boost programming operation, a drain-side self boost programming operation, a modified drain-side self boost programming operation, a source-side self boost programming operation, a modified source-side self boost programming operation and a virtual ground programming operation.

9. The method of claim 4, wherein the non-volatile memory cell is one of a floating gate memory cell, a multi-level cell (MLC), and a non-conductive floating node memory cell.

10. The method of claim 4, wherein the method is part of an erase operation.

11. A method of drain-side self boost programming in a NAND architecture memory device, comprising:

applying a program voltage to a selected word line coupled to a non-volatile memory cell of the NAND architecture memory string that is selected for programming;

applying a cutoff voltage to a first set of two or more unselected word lines, wherein the first set of two or more word lines are directly adjacent to each other and where the first set of two or more unselected word lines are between the selected word line and a source line; and

applying a pass voltage to one or more remaining word lines of the memory string.

12. The method of claim 11, wherein the cutoff voltage is between Vcc and ground or Vdd and Vss.

13. The method of claim 11, further comprising:

applying a second pass voltage to a second set of one or more unselected word lines, wherein the second set of one or more unselected word lines are between the first set of two or more unselected word lines and the selected word line, and where the second pass voltage is between the pass voltage and a ground potential.

14. The method of claim 11, wherein the drain-side self boost is a local self boost that further comprises:

applying a cutoff voltage to a third set of two or more unselected word lines, wherein the third set of two or more word lines are directly adjacent to each other and where the third set of two or more unselected word lines are between the selected word line and a bit line.

15. The method of claim 14, further comprising:

applying a second pass voltage to a fourth set of one or more unselected word lines, wherein the fourth set of one or more unselected word lines are between the first and third sets of two or more unselected word lines and the selected word line, and where the second pass voltage is between the pass voltage and a ground potential.

16. The method of claim 14, wherein the first and/or third sets of two or more unselected word lines are physically adjacent the selected word line.

17. A non-volatile NAND architecture memory device comprising:

a NAND architecture non-volatile memory array having a plurality of memory blocks; and

a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by,

applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string of the array that is selected for programming;

applying a cutoff voltage to at least one first set of two or more word lines, wherein the set of two or more word lines are directly adjacent to each other; and

applying a first pass voltage to one or more remaining word lines between the set of one or more source-side adjacent word lines and the source line.

18. The non-volatile NAND architecture memory device of claim 17, wherein the control circuit is adapted to apply a second pass voltage to a second set of one or more unselected word lines, wherein the second set of one or more unselected word lines are between the at least one first set of one or more unselected word lines and the selected word line, and where the second pass voltage is between the first pass voltage and a ground potential.

19. The non-volatile NAND architecture memory device of claim 18, wherein the second pass voltage is one of a read pass voltage (Vpass_read) and a read select voltage (Vselect_read).

20. The non-volatile NAND architecture memory device of claim 17, wherein the control circuit is adapted to program memory cells by one of a drain-side self boost programming operation, a modified drain-side self boost programming operation, a local self boost programming operation, a modified local self boost programming operation, a source-side self boost programming operation, a modified source side self boost programming operation, and a virtual ground programming operation.

21. A system comprising:

a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,

a NAND architecture non-volatile memory array having a plurality of blocks;

wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by,

applying a program voltage to a selected word line coupled to a non-volatile memory cell of a NAND architecture memory string of the array that is selected for programming;

applying a cutoff voltage to at least one first set of two or more word lines, wherein the set of two or more word lines are directly adjacent to each other; and

applying a first pass voltage to one or more remaining word lines between the set of one or more source-side adjacent word lines and the source line.

22. The system of claim 21, wherein the host is one of a processor and a memory controller.

23. The system of claim 21, wherein the system is adapted to apply a second pass voltage to a second set of one or more unselected word lines, wherein the second set of one or more unselected word lines are between the at least one first set of one or more unselected word lines and the selected word line, and where the second pass voltage is between the first pass voltage and a ground potential.

24. The system of claim 21, wherein the system is adapted to program memory cells by one of a drain-side self boost programming operation, a modified drain-side self boost programming operation, a local self boost programming operation, a modified local self boost programming operation, a source-side self boost programming operation, a modified source side self boost programming operation, and a virtual ground programming operation.

25. The system of claim 21, wherein a non-volatile memory device is a memory module.